Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

Abstract: An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlxGayInzN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped Alx?Gay?Inz?N channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlxGayInzN gate layer comprises the steps of: (a1) growing the first part above the p-doped Alx?Gay?Inz?N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3×1019 atoms/cm3, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3×1019 atoms/cm3 and having a top surface having a Mg concentration higher than 6×1019 atoms/cm3.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including an epitaxial layer; a transition layer connected to the epitaxial layer; and a bypass component connected to the transition layer; the unipolar component and the bypass component are connected in parallel and the transition layer is configured between the unipolar component and the bypass component.

Abstract: A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

Abstract: An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion, a pad portion and a protrusion. The electrode portion is parallel to a top surface of the substrate, extending in a first direction. The pad portion extends from the electrode portion in an inclined direction with respect to the top surface of the substrate. The protrusion protrudes from a portion of the pad portion in a direction parallel to the inclined direction. Protrusions of the plurality of electrodes are arranged in a direction diagonal to the first direction when viewed from a plan view.

Abstract: Methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: A flexible display substrate, a method for manufacturing the same, a flexible display panel, and a flexible display device. The flexible display substrate includes: a flexible base substrate including a bendable region and an unbendable region, the bendable region including a bendable edge and an unbendable edge, the unbendable edge extending in a first direction; and at least one transistor in the bendable region of the flexible base substrate, including a gate electrode, a source region, a drain region, and an active layer, wherein the active layer extends in a direction substantially parallel to the first direction.

Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. Opposing edges of the upper card are located between vertical planes defined by the outer sidewalls of the upper portion of the casing.

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area.

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

Abstract: A device for switchably influencing electromagnetic radiation includes a phase change material and an optically responsive structure. The phase change material is switchable between at least a first state and a second state. The first state and the second state have different electrical and/or magnetic properties. The optically responsive structure is in contact with the phase change material and has at least a first nanostructure and a second nanostructure. The first nanostructure is being different from the second nanostructure. The first nanostructure is optically responsive at a predetermined electromagnetic wavelength when the phase change material is in its first state, and non-responsive at the predetermined wavelength when the phase change material is in its second state.

Abstract: A method for enhancing visual representation of a geologic feature in 3D seismic survey data, comprising the steps of: (a) generating a plurality of first attribute volumes, each comprising at least one characterising attribute, derivable from said 3D seismic data and different from the characterising attributes of any one of the other said plurality of first attribute volumes; (b) generating a plurality of filtered attribute volumes for each one of said plurality of first attribute volumes, utilizing a plurality of distinct filter settings at each one of said at least one characterising attribute; (c) generating a composite attribute volume by selectively combining one or more of said plurality of filtered attribute volumes so as to maximise visual detectability of said geologic feature.

Abstract: The present invention provides an array substrate, a method for manufacturing the same and a display device. The array substrate includes a substrate; a anode layer and a pixel defining layer on the substrate; an auxiliary cathode layer on the pixel defining layer; a spacer layer on the auxiliary cathode layer; an organic light-emitting layer covering the anode layer, the pixel defining layer, and the spacer layer; a cathode layer covering the organic light-emitting layer, wherein the cathode layer laps with the auxiliary cathode layer on the pixel defining layer. Since the auxiliary cathode layer disposed on the pixel defining layer corresponds to the non-display area, the material with low resistivity can be selected for the auxiliary cathode layer. Thus the uniformity of the display brightness and the like of the screen can be improved, thereby improving the display quality of the screen.

Abstract: The present disclosure provides a thin film transistor and a method of preparing the same. The thin film transistor includes a substrate; a gate provided on the substrate; a gate insulating layer provided on the substrate and completely covering the gate; a semiconductor layer provided on the gate insulating layer; and an etch stop layer and a source/drain electrode layer provided on the semiconductor layer. The etch stop layer includes a first stop layer provided on a side of the channel region, the side being away from the gate, and a second stop layer provided on the first stop layer. The thin film transistor and the method for preparing the same as proposed in the present disclosure can prevent the device from being damaged by a high temperature and reduce the film-forming time and increase productivity; the SiO2 can be prepared at a lower temperature.