Abstract: An electroluminescent display device includes a substrate on which a display area and a non-display area are defined. A thin film transistor is in the display area on the substrate. A light-emitting diode is connected to the thin film transistor and includes a first electrode, a light-emitting layer and a second electrode. A first link line is disposed in the non-display area and applies a first voltage to the first electrode. A second link line is spaced apart from the first link line in the non-display area. A conductive pattern is disposed in the non-display area and is connected to the second electrode to apply a second voltage. The conductive pattern has an opening corresponding to the first and second link lines.

Abstract: A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.

Abstract: A substrate processing apparatus includes: a reaction tube with a process chamber defined therein, the process chamber being configured to process a substrate; a heating device configured to heat the process chamber; a gas supply part configured to supply a process gas used in processing the substrate; and a plasma generating part including an electrode composed of a first electrode portion connected to a high frequency power supply and a second electrode portion grounded to the earth, which are installed to surround the entire circumference of an outer wall of the reaction tube. An inter-electrode distance between the first electrode portion and the second electrode portion is determined by at least a frequency of the high frequency power supply and a voltage applied across the electrode. The first and second electrode portions are installed based on the determined inter-electrode distance.

Abstract: In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.

Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.

Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

Abstract: A device is provided that includes a semiconductor substrate on which a free magnetic element is positioned, which has first and second magnetic domains separated by a domain wall. A first magnet is positioned on the substrate near a first end of the free magnetic element, and has a first polarity and a first value of coercivity. A second magnet is positioned on the substrate near a second end of the free magnetic element, and has a second polarity, antiparallel relative to the first polarity, and a second value of coercivity different from the first value of coercivity.

Abstract: The present disclosure relates to a sensor comprising: an array of photodetectors comprising a first subarray of at least one photodetector and a second subarray of at least one photodetector; a first optical arrangement to direct incoming photons toward the first subarray; and a second optical arrangement to direct incoming photons toward the second subarray.

Abstract: An electroluminescent device comprising a first electrode; a hole transport layer disposed on the first electrode; an emission layer disposed on the hole transport layer and comprising a plurality of light emitting particles; an electron transport layer disposed on the emission layer and comprising a metal oxide particle-organic polymer composite comprising a plurality of metal oxide particles and an organic polymer; and a second electrode disposed on the electron transport layer, wherein the organic polymer is present in the metal oxide particle-organic polymer composition in an amount of about 7 weight percent to about 30 weight percent based on a total weight of the electron transport layer.

Abstract: A microscale device may include a patterned forest of vertically grown and aligned carbon nanotubes defining a carbon nanotube forest with the nanotubes having a height defining a thickness of the forest. The patterned forest may define a patterned frame that defines one or more components of the microscale device. The microscale device may also include a conformal coating of substantially uniform thickness extending throughout the carbon nanotube forest. The carbon nanotube forest may have a thickness of at least three microns. The conformal coating may substantially coat the nanotubes, define coated nanotubes and connect adjacent nanotubes together such that the carbon nanotube forest is sufficiently robust for liquid processing, without substantially filling interstices between individual coated nanotubes. The microscale device may also include a metallic interstitial material infiltrating the carbon nanotube forest and at least partially filling interstices between individual coated nanotubes.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes: forming a pixel electrode on a substrate; forming a pixel-defining layer (PDL) having an opening exposing at least a part of the pixel electrode; forming an intermediate layer including a central portion disposed on the pixel electrode, an edge portion that extends from the central portion and contacts the PDL, at least one common layer, and an organic emission layer; forming a protective layer including a central portion disposed on the central portion of the intermediate layer and an edge portion that extends from the central portion of the protective layer and contacts the PDL; and forming an opposite electrode on the PDL, the opposite electrode having an opening exposing at least a part of the protective layer and electrically connected to the protective layer.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.

Abstract: In a transistor including an oxide semiconductor film, field-effect mobility and reliability are improved. A semiconductor device includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same elements. The second oxide semiconductor film includes a region having a higher carrier density than the first oxide semiconductor film and the third oxide semiconductor film.

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: A semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The transistor includes an oxide semiconductor. The amount of oxygen released from the second insulator when converted into oxygen molecules is larger than or equal to 1×1014 molecules/cm2 and smaller than 1×1016 molecules/cm2 in thermal desorption spectroscopy at a surface temperature of a film of the second insulator of higher than or equal to 50° C. and lower than or equal to 500° C. The second insulator includes oxygen, nitrogen, and silicon.

Abstract: A semiconductor device package includes a carrier, a wall disposed on a top surface of the carrier, a cover, and a sensor element. The cover includes a portion protruding from a bottom surface of the cover, where the protruding portion of the cover contacts a top surface of the wall to define a space. The sensor element is positioned in the space.

Abstract: A display apparatus includes: a substrate having a bending area between a first area and a second area; an inorganic insulating layer arranged on the substrate, the inorganic insulating layer having an opening or a groove corresponding to the bending area; a wiring unit extending to the second area through the bending area, the wiring unit arranged on the inorganic insulating layer and at least a portion thereof overlapping the opening or the groove; and an organic material layer between the inorganic insulating layer and the wiring unit, the organic material layer configured to fill the opening or the groove, wherein the wiring unit comprises a first wire and a second wire that are adjacent to each other, and a width in which the opening or the groove overlaps the first wire is different from the width in which the opening or the groove overlaps the second wire.

Abstract: To provide a semiconductor device with favorable electrical characteristics. To provide a method for manufacturing a semiconductor device with high productivity. To reduce the temperatures in a manufacturing process of a semiconductor device. An island-like oxide semiconductor layer is formed over a first insulating film; a second insulating film and a first conductive film are formed in this order, covering the oxide semiconductor layer; oxygen is supplied to the second insulating film through the first conductive film; a metal oxide film is formed over the second insulating film in an atmosphere containing oxygen; a first gate electrode is formed by processing the metal oxide film; a third insulating film is formed, covering the first gate electrode and the second insulating film; and first heat treatment is performed. The second insulating film and the third insulating film each include oxide. The highest temperature in the above steps is 340° C. or lower.