Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Abstract: A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.

Abstract: In a semiconductor pressure sensor element, a first hydrogen permeation protection film is provided on a principal surface side of a first silicon substrate, and a second hydrogen permeation protection film is provided on a principal surface side of a second silicon substrate. The permeation paths of the hydrogen fluxes shown by the arrows A and B in FIG. 9 are blocked by the films. Also, a trench surrounding a reference pressure chamber is provided, and the first hydrogen permeation protection film and a third hydrogen permeation protection film are joined at the bottom portion of the trench, thereby blocking the permeation path of the hydrogen flux shown by the arrow C in FIG. 9. Furthermore, by providing a hydrogen storage chamber, hydrogen is trapped before the hydrogen reaches the reference pressure chamber.

Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

Abstract: A method for forming a microscale device may include growing, by a chemical vapor deposition, a patterned forest of vertically aligned carbon nanotubes, wherein the patterned forest defines a component of the microscale device, and applying a conformal non-metal coating to the vertically aligned carbon nanotubes throughout the patterned forest, wherein the conformal non-metal coating comprises a substantially uniform thickness along a length of the vertically aligned carbon nanotubes.

Abstract: An optoelectronic assembly comprising an optoelectronic component, which comprises a specularly reflective surface and comprising a radiation cooler in direct physical contact with the optoelectronic component. The radiation cooler is arranged above the specularly reflective surface.

Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.

Abstract: A MEMS device package comprising a first die of semiconductor material including a contact pad and a second die of semiconductor material stacked on the first die. The second die is smaller than the first die. The second die includes a contact pad, and a conductive wire is coupled between the contact pad of the first die and a contact pad of the second die. A mold compound is on the second die and the first die. A vertical connection structure is on the contact pad of the second die. The vertical connection structure extends through the mold compound.

Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Abstract: A display panel may include an insulating substrate having a display region and a peripheral region adjacent to the display region; a plurality of insulating layers on the insulating substrate; a pixel on the display region, the pixel including a thin-film transistor and an organic light emitting device connected to the thin-film transistor; and a crack dam on the peripheral region and spaced apart from the pixel. The crack dam may be disposed adjacent to one of side surfaces of the insulating substrate extending in a first direction. The crack dam may include a plurality of insulating patterns, which are extended in the first direction and are spaced apart from each other in a second direction crossing the first direction, and a plurality of conductive patterns, which are disposed to fill gap regions between the insulating patterns.

Abstract: The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.

Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

Abstract: A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Abstract: A mount (10) and an optoelectronic component (100) with the mount (10) are provided, wherein the mount (10) comprises a moulding (5), at least one through-contact (41, 42) and a plurality of reinforcing fibres (52), wherein the moulding (5) is formed from an electrically insulating moulding material (53), the through-contact (41, 42) is formed from an electrically conductive material, and the reinforcing fibres (52) produce a mechanical connection between the moulding (5) and the through-contact (41, 42) by the reinforcing fibres (52) being arranged in certain regions of the moulding (5) and arranged in certain regions of the through-contact (41, 42). A method for producing a mount or a component with such a mount is also provided.

Abstract: A metal oxide film containing a crystal part is provided. Alternatively, a metal oxide film with highly stable physical properties is provided. Alternatively, a metal oxide film with improved electrical characteristics is provided. Alternatively, a metal oxide film with which field-effect mobility can be increased is provided. A metal oxide film including In, M (M is Al, Ga, Y, or Sn), and Zn includes a first crystal part and a second crystal part; the first crystal part has c-axis alignment; the second crystal part has no c-axis alignment; and the existing proportion of the second crystal part is higher than the existing proportion of the first crystal part.

Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.