Patents Examined by Stephen W. Smoot
  • Patent number: 10734500
    Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
  • Patent number: 10734552
    Abstract: An embodiment provides a semiconductor device including a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a plurality of recesses passing through the second conductive semiconductor layer and the active layer and extending to a portion of the first conductive semiconductor layer; a plurality of first electrodes disposed inside the plurality of recesses and electrically connected with the first conductive semiconductor layer; and a second electrode electrically connected with the second conductive semiconductor layer, wherein a ratio of a first area of where the plurality of first electrodes are in contact with the first conductive semiconductor layer and a second area of where the second electrode is in contact with the second conductive semiconductor layer (first area:second area) ranges from 1:3 to 1:10.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Su Ik Park, Youn Joon Sung, Min Sung Kim, Yong Gyeong Lee, Eun Dk Lee
  • Patent number: 10734503
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu
  • Patent number: 10734262
    Abstract: Systems and methods for substrate support in a millisecond anneal system are provided. In one example implementation, a millisecond anneal system includes a processing chamber having a wafer support plate. A plurality of support pins can extend from the wafer support plate. The support pins can be configured to support a substrate. At least one of the support pins can have a spherical surface profile to accommodate a varying angle of a substrate surface normal at the point of contact with the substrate. Other example aspects of the present disclosure are directed to methods for estimating, for instance, local contact stress at the point of contact with the support pin.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 4, 2020
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventor: Joseph Cibere
  • Patent number: 10727217
    Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10727064
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10720582
    Abstract: There is disclosed a resistance change memory device according to an aspect of the present disclosure. The resistance change memory device includes a first electrode layer and a second electrode layer that are disposed to be spaced apart from each other, and a resistance change material layer disposed between the first and second electrode layers and including an amorphous carbon structure. The resistance change material layer includes an impurity element adhering to the amorphous carbon structure, and the impurity element has a concentration gradient along a thickness direction of the resistance change material layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Sanghun Lee
  • Patent number: 10714678
    Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Park, Woo-Jin Kim, Jeong-Heon Park, Se-Chung Oh, Joon-Myoung Lee, Hyun Cho
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10710210
    Abstract: A method for forming semiconductor devices includes: grinding a backside of a semiconductor wafer with a grinding wheel during a first time interval, wherein the grinding wheel is forward moved during the first time interval, wherein a plurality of semiconductor devices are formed on the semiconductor wafer; polishing the backside of the semiconductor wafer with the grinding wheel in a second time interval, wherein the grinding wheel is backward moved during the second time interval; and dicing the semiconductor wafer to separate the plurality of semiconductor devices from each other without additional polishing of the backside of the semiconductor wafer before dicing the semiconductor wafer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: July 14, 2020
    Assignee: Infineon Technologies AG
    Inventor: Rudolf Lehner
  • Patent number: 10714570
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10714473
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10714524
    Abstract: The present disclosure relates to a circuit board, a semiconductor device, an imaging device, a solid-state image sensor, a method for manufacturing a solid-state image sensor, and an electronic apparatus that suppress a decrease in characteristics and a yield. A step portion formed on a substrate surface is configured in a divided state. With this configuration, a photoresist liquid dropped in a lithography process flows through a gap between the divided step portions so that the photoresist liquid uniformly flows on an imaging surface, whereby a decrease in characteristics and a yield due to application unevenness can be suppressed. The present disclosure can be applied to a solid-state image sensor.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 14, 2020
    Assignee: SONY CORPORATION
    Inventor: Kenji Takeo
  • Patent number: 10710873
    Abstract: Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 14, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
  • Patent number: 10714344
    Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 10707319
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Patent number: 10700129
    Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10?8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee
  • Patent number: 10700110
    Abstract: A fan-out sensor package includes: a substrate in which a through-hole is formed and portions of a wiring layer are exposed from an insulating layer; an image sensor having an active surface having a sensing region disposed below the through-hole of the substrate and connection pads disposed in the vicinity of the sensing region; an optical member disposed on the active surface of the image sensor; a dam member disposed in the vicinity of the sensing region; and an encapsulant encapsulating the substrate and the image sensor, wherein the third wiring layer and the connection pads are electrically connected to each other by connection members.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hyun Lim, Yoon Seok Seo, Kyung Moon Jung, Eun Jin Kim
  • Patent number: 10700268
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande
  • Patent number: 10693005
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran