Patents Examined by Stephen W. Smoot
  • Patent number: 10388509
    Abstract: A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 20, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 10381561
    Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 13, 2019
    Assignee: Internatoinal Business Machines Corporation
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs
  • Patent number: 10381217
    Abstract: In a method of deposition a thin film, a substrate having a pattern may be provided. A surface of the substrate may be treated using a deposition-suppressing gas to form a deposition-suppressing layer on the pattern. A process gas may be applied to the pattern to deposit the thin film. The deposition-suppressing gas may include fluorine.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 13, 2019
    Assignee: WONIK IPS CO., LTD.
    Inventors: Byung Chul Cho, Sang Jin Lee, In Hwan Yi, Kwang Seon Jin
  • Patent number: 10378159
    Abstract: The present invention relates to the detection of a short term irregularity under a driving vehicle having a first wheel, by determining a first sensor signal indicative of time dependent vibrations at the first wheel, using a first sensor; determining a second sensor signal indicative of a vertical movement the vehicle chassis, using a second sensor; and detect a short term irregularity of a road surface under the driving vehicle based on the first sensor signal and the second sensor signal.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: August 13, 2019
    Assignee: NIRA DYNAMICS AB
    Inventors: Thomas Svantesson, Robert Johansson, Olle Noren
  • Patent number: 10381480
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10373841
    Abstract: A photomask manufacturing method relating to semiconductor technology is presented. The manufacturing method involves providing a substrate structure comprising an etch material layer, a first sacrificial layer on a portion of the etch material layer, and a photomask layer on an upper surface of the etch material layer and on an upper surface and a side surface of the first sacrificial layer; forming a second sacrificial layer covering the photomask layer on the etch material layer and on the side surface of the first sacrificial layer; etching the photomask layer not covered by the second sacrificial layer to expose the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and removing the photomask layer on the etch material layer. This photomask manufacturing method offers a photomask of better symmetricity than those from conventional methods.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 6, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Hai Yang Zhang, Yan Wang
  • Patent number: 10373825
    Abstract: Disclosed is a method of fabricating a gallium nitride substrate using nanoparticles with a core-shell structure. A method of fabricating a gallium nitride substrate using nanoparticles with a core-shell structure according to an embodiment of the present disclosure includes a step of coating nanoparticles with a core-shell structure on a temporary substrate to form at least one nanoparticle layer; a step of allowing a pit gallium nitride (pit GaN) layer to grow on the temporary substrate; a step of allowing a mirror GaN layer (mirror GaN) to grow on the pit GaN layer; and a step of separating the temporary substrate, wherein each of the nanoparticles with a core-shell structure includes a core and an ionic polymer shell coated on a surface of the core surface.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 6, 2019
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Tae Hun Shim, Jae Hyoung Shim, Il Hwan Kim
  • Patent number: 10371874
    Abstract: The present disclosure relates to a substrate unit of a nanostructure assembly type, an optical image apparatus including the same, and a controlling method thereof, and the substrate unit of the nanostructure assembly type according to an exemplary embodiment includes: a lower substrate; an upper substrate separated from the lower substrate, an observation object being able to be positioned at the upper substrate; and at least one metal nanostructure positioned on the lower substrate, wherein the at least one metal nanostructure is capable of being assembled on the lower substrate or separated from the lower substrate.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 6, 2019
    Assignee: YONSEI UNIVERSITY, UNIVERSITY—INDUSTRY FOUNDATION (UIF)
    Inventors: Donghyun Kim, Wonju Lee, Hongki Lee, Taehwang Son
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10354991
    Abstract: An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first supply voltage, a second detection circuit coupled to a second supply voltage, and a rail clamp device. During a first type of electrical stress event, the rail clamp device is activated in response to a first output signal provided by the first detection circuit. During a second type of electrical stress event, the rail clamp device is activated in response to a second output signal provided by the second detection circuit.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 16, 2019
    Assignee: NXP USA, Inc.
    Inventors: Robert Matthew Mertens, Michael A. Stockinger, Alexander Paul Gerdemann
  • Patent number: 10347530
    Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate, the dielectric layer having an opening extending to the substrate. The method further includes forming a mask layer on at least one portion of the dielectric layer, forming a metal layer filling the opening and covering portions of dielectric layer not covered by the mask layer, removing the mask layer, and planarizing the metal layer so that an upper surface of a remaining portion of the metal layer is flush with an upper surface of the dielectric layer. The method can mitigate the warping problems of the substrate associated with the fabrication of the interconnect structure.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Ji Guang Zhu, Hai Ting Li
  • Patent number: 10340361
    Abstract: A MOS transistor manufacturing method, including: forming a first conductive or semiconductor layer; forming a sacrificial gate on the first layer and a second layer made of an insulating material laterally surrounding the sacrificial gate; forming, on either side of the sacrificial gate, source and drain electric connection elements crossing the second layer and contacting the first layer; removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate; depositing a third layer made of a two-dimensional semiconductor material; depositing a fourth layer made of an insulating material on the third layer; and forming a conductive gate in the opening, on the fourth layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 2, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Fabrice Nemouchi, Yves Morand
  • Patent number: 10334960
    Abstract: A system and method for incorporating occupancy-detecting technology into furniture is provided. More particularly, the invention relates to detecting occupancy in a recliner using a sinuous wire detection array incorporated into a seat. Further embodiments of the invention are directed to a system and method for incorporating capacitance detection technology with one or more conductive features of a recliner mechanism. In some aspects, a sensor is provided based on coupling one or more conductive features to a control component of the capacitance detector control component. A controller may determine the corresponding response based on occupancy detection and/or presence detection. A processor may receive information regarding changes in capacitance and determines when a change in voltage satisfies a threshold. Based on a determination of occupancy and/or presence, a variety of corresponding features of the adjustable recliner may be activated.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 2, 2019
    Assignee: L&P Property Management Company
    Inventors: Ryan Edward Chacon, William Robert Rohr, Avinash Madadi, Gregory Mark Lawson
  • Patent number: 10332746
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10326025
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10326015
    Abstract: A switching element may include a semiconductor substrate, first and second trenches, a gate insulating layer, an interlayer insulating layer covering the semiconductor substrate, and an electrode on the interlayer insulating layer. A wide portion and a narrow portion may be arranged alternately between the first and second trenches. The interlayer insulating layer may include a contact hole in the wide portion. The electrode may be in contact with the semiconductor substrate within the contact hole. The semiconductor substrate may include an upper n-type region in contact with the gate insulating layer in the narrow portion and in contact with the electrode, a p-type body contact region in contact with the electrode, a p-type body region in contact with the gate insulating layer in the narrow portion, and a lower n-type region in contact with the gate insulating layer in the narrow portion.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masatoshi Tsujimura, Katsuhiro Kutsuki, Sachiko Aoi, Yasushi Urakami
  • Patent number: 10319659
    Abstract: Implementations of semiconductor packages may include: a substrate comprising a first side and a second side and a hole in the substrate. The hole extending from the first side to the second side of the substrate and positioned in a center of the substrate. The semiconductor packages may also include a bushing around the hole to the first side of the substrate. The semiconductor packages may also include a plurality of pin holders arranged and coupled on the substrate. The semiconductor package may also include a molding compound at least partially encapsulating the substrate, encapsulating a side surface of the bushing, and encapsulating a plurality of side surfaces of the plurality of pin holders.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, C H Chew, Yushuang Yao
  • Patent number: 10319731
    Abstract: The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita, Kangguo Cheng
  • Patent number: 10319759
    Abstract: An image pickup element mounting substrate includes: a frame body composed of an insulating layer, a through hole being defined by an internal periphery of the frame body; an electronic component mounted on a lower surface side of the frame body; and a flat plate which is disposed on a lower surface of the frame body and covers an opening of the through hole while being partly kept in out-of-contact with the electronic component, the flat plate including an image pickup element mounting section at a part of an upper surface thereof which part is surrounded by the frame body, a lower surface of the electronic component being located above a level of a lower surface of the flat plate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 11, 2019
    Assignee: Kyocera Corporation
    Inventors: Takuji Okamura, Akihiko Funahashi
  • Patent number: 10312150
    Abstract: Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fuad Al-Amoody, Jinping Liu, Joseph Kassim, Bharat Krishnan