Patents Examined by Stephen W. Smoot
  • Patent number: 11075360
    Abstract: An OLED display panel, a display device and a method for manufacturing the OLED display panel are provided. The display panel includes a display panel body, and an encapsulation layer disposed on the display panel body and applied to encapsulate the display panel body. The encapsulation layer has a gradually increasing thickness in a direction from a central position of the display panel to an edge position of the display panel.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: July 27, 2021
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Qingyu Huang, Zhiqiang Jiao, Zhongyuan Sun, Xiang Zhou
  • Patent number: 11075241
    Abstract: The present technology relates to a solid-state imaging device that includes a sensor substrate having at least a first pixel region and a second pixel region, and a light shielding body substrate which is stacked on an upper surface of the sensor substrate and has a light shielding body surrounding a plurality of light guide paths, in which the plurality of light guide paths includes at least a first light guide path corresponding to the first pixel region, and a second light guide path corresponding to the second pixel region, a plurality of pixels included in the first pixel region has a light shielding structure based on respective pixel positions in the first pixel region, and a plurality of pixels included in the second pixel region has a light shielding structure based on respective pixel positions in the second pixel region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 27, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Harumi Tanaka
  • Patent number: 11069819
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A gate electrode has a section that is wrapped about a first side surface and a second side surface of a mandrel that is composed of a dielectric material. A channel layer has a channel region that is positioned in part between the first side surface of the mandrel and the section of the gate electrode. The channel layer is composed of a two-dimensional material.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventor: Julien Frougier
  • Patent number: 11069531
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11069801
    Abstract: A semiconductor device, an electronic apparatus, and a method of manufacturing a semiconductor device with reduced RTN influence regardless of gate electrode shape are disclosed. In one example, a semiconductor device includes a substrate having an element region and an element separating region, the element region including a source region and a drain region, and a channel region between the source and drain regions. The element separating region is arranged on both sides in a direction orthogonal to the source, channel and drain region arrangement direction. A gate insulating film is provided on the element region of the substrate from one side to another side of the element separating region. A gate electrode is provided on the gate insulating film, and includes an impurity having a different concentration in a boundary region as compared to a central region.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 20, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 11069814
    Abstract: An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including: a gate electrode disposed on a substrate, a first insulating film disposed on the gate electrode, an active layer disposed on the first insulating film, the active layer including: a first portion of the active layer overlapping with an upper surface of the gate electrode, a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and a third portion of the active layer extending from the second portion of the active layer, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode, a second insulating film disposed on the active layer, a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active l
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SangYun Sung, SeHee Park, Jiyong Noh, InTak Cho, PilSang Yun
  • Patent number: 11069843
    Abstract: A light-emitting device includes: a light-emitting element; a first light-diffusion layer disposed laterally to the light-emitting element and constituting a first portion of lateral surfaces of the light-emitting device; a second light-diffusion layer disposed above the light-emitting element and the first light-diffusion layer and constituting a second portion of the lateral surfaces of the light-emitting device; a light-control portion disposed between the first light-diffusion layer and the second light-diffusion layer and configured to reflect a portion of light emitted from the light-emitting element; and a first light-reflection layer disposed on the second light-diffusion layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 20, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Toru Hashimoto
  • Patent number: 11069572
    Abstract: Semiconductor device and formation method are provided. The method includes providing a substrate, a first fin and a second fin on the substrate, an isolation structure covering a portion of sidewalls of the first and second fins, a gate structure across the first fin or the second fin, a first doped source/drain region in the first fin, a second doped source/drain region in the second fin, and an interlayer dielectric layer on the isolation structure, the first and second fins, and the gate structure. A first through hole is formed in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region. A second through hole is formed in the interlayer dielectric layer on the isolation structure to connect to the first through hole. A first plug is formed in the first through hole and a second plug is formed in the second through hole.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Ze Jun He, Jun Ling Pang
  • Patent number: 11063151
    Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Daniel B. Bergstrom, Christopher J. Wiegand
  • Patent number: 11056527
    Abstract: Described herein are photon counting devices comprising direct mode detectors with improved signal to noise ratios which are suitable for use in X-ray imaging devices, and other imaging devices.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: July 6, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Jinbo Cao, Jongwoo Choi, Aharon Yakimov
  • Patent number: 11056397
    Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Elliot Tan
  • Patent number: 11056396
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wu, Ming-Hung Han, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 11049784
    Abstract: A semiconductor device comprising a first and second doped semiconductor layer wherein the first layer is a monosilicon layer and the second layer is a polysilicon layer, an oxide layer covering the first and second layer, and an interconnect which electrically connects the first and second layer comprises a metal alloy which has a first part in contact with the first layer and a second part in contact with the second layer, wherein a part of the metal alloy between the first and the second part crosses over a sidewall of the second layer; at least one electronic component is formed in the first and/or second layer; the semiconductor device moreover comprises a stoichiometric passivation layer which covers the first and second layer and the oxide layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 29, 2021
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventor: Appolonius Jacobus Van Der Wiel
  • Patent number: 11049901
    Abstract: A display apparatus comprises a thin-film transistor array disposed on a substrate; a plurality of electro-luminescence devices disposed on the thin-film transistor array; a plurality of light-receiving devices disposed on the thin-film transistor array and spaced apart from the plurality of electro-luminescence devices; a plurality of light shield patterns shielding the plurality of light-receiving devices; and at least one opening pattern arranged in each light shield pattern that has a predetermined opening direction.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 29, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungpil Ryu, Hyung-Seok Bang, Eunju Kim
  • Patent number: 11049899
    Abstract: A structure and a method for packaging an image sensor chip. The structure includes: an image sensor chip and a substrate. The image sensor chip includes a first surface and a second surface that are opposite to each other, and the first surface is provided with multiple pixels configured to collect image information and multiple first bonding pads connected with the multiple pixels. The substrate covers the first surface of the image sensor chip, and is provided with wiring and a contact terminal connected with the wiring. A periphery of the image sensor chip is bonded to the substrate via an anisotropic conductive adhesive, the multiple first bonding pads are electrically connected with the contact terminal via the anisotropic conductive adhesive, and the anisotropic conductive adhesive surrounds all the multiple pixels and is not overlapped with the multiple pixels in a direction perpendicular to the substrate.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 29, 2021
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhiming Geng
  • Patent number: 11041242
    Abstract: A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Hui Huang, Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 11043571
    Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 22, 2021
    Assignee: ACORN SEMI, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 11043612
    Abstract: A DUV-LED including a bottom substrate, a n-contact/injection layer formed on the bottom substrate, a p-contact region, and an emitting active region between the n-contact/injection layer and the contact region. The emitting active region includes at least one GaN quantum heterostructure. The at least one GaN quantum heterostructures is sized and shaped to determine a certain emission wavelength. Preferably, the certain emission wavelength is in a range of approximately 219-280 nm. In one embodiment, the size is controlled by precisely controlling parameters selected from the group consisting of: an epitaxial deposition time; a Ga/N ratio; a thermal annealing time; a temperature during deposition; and combinations thereof.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 22, 2021
    Assignee: Cornell University
    Inventors: SM Islam, Vladimir Protasenko, Huili Grace Xing, Debdeep Jena, Jai Verma
  • Patent number: 11043576
    Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11037974
    Abstract: An optical sensor in an integrated Complementary Metal Oxide Semiconductor, CMOS, device, the sensor including a sensor element with an optical active region and a CMOS backend stack including one or more layers. The sensor further includes an optical lens formed in a layer of the one or more layers and arranged to direct light incident upon it towards the sensor element.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 15, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventors: Alexander Zimmer, Daniel Gabler, Matthias Krojer