Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon nitride layer deposited by plasma deposition.

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

Abstract: An electro-luminescence display apparatus comprises a transparent substrate; a thin-film transistor array disposed on the transparent substrate; a first electrode disposed on the thin-film transistor array; an electro-luminescence diode disposed on the first electrode; a second electrode disposed on the electro-luminescence diode; an encapsulation unit disposed on the second electrode; and an external light-absorbing layer disposed on the encapsulation unit and absorbing external light that passes through the transparent substrate.

Abstract: An efficient wide bandgap GaN-based LED chip based on a surface plasmon effect and a manufacturing method therefor. The efficient wide bandgap GaN-based LED chip is of a flip-chip structure, and comprises, from bottom to top in sequence, a substrate, a buffer layer, an unintentionally doped GaN layer, an n-GaN layer, a quantum well layer, an electron blocking layer, a p-GaN layer, a metallic reflecting mirror layer, a passivation layer, a p-electrode layer, an n-electrode layer; and a position of a bottom surface of the metallic reflecting mirror layer connected to a surface of the p-GaN layer is provided with a micro-nano composite metal structure. A micro metal structure comprises alternating protrusion portions and recess portions; and a nano metal structure is distributed on an interface of the micro metal structure and the p-GaN layer.

Abstract: An integrated circuit (IC), including a first integrated circuit (IC) cell configured to perform a defined operation on a first input signal to generate a first output signal, wherein the first IC cell includes a first metal configured to receive the first input signal or output the first output signal; and a second IC cell configured to perform the defined operation on a second input signal to generate a second output signal, wherein the second IC cell includes a second metal configured to receive the second input signal or the second output signal, wherein the second metal is located substantially in the same location within the second IC cell as the first metal is located within the first IC cell, and wherein the first and second metals are configured differently based on differences in first and second intercell metal interconnects to which the first and second metals electrically connect, respectively.

Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.

Abstract: A method of making a semiconductor device includes depositing a first polysilicon layer over a substrate. The method further includes forming a barrier layer over the first polysilicon layer. The method further includes patterning the first polysilicon layer. The method further includes depositing a second polysilicon layer over the barrier layer, wherein the depositing of the second polysilicon layer includes increasing a grain size of the first polysilicon layer, and causing at least one grain boundary in the first polysilicon layer to contact the barrier layer.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A photoelectric conversion device has an isolation structure. First and second isolation portions are provided between first and second photoelectric conversion elements. The first isolation portion extends from a first plane of a semiconductor layer to a position corresponding to at least a quarter of a length from the first plane to a second plane of the semiconductor layer. The second isolation portion extends from the second plane of the semiconductor layer to a position corresponding to at least a quarter of the length from the first plane to the second plane.

Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

Abstract: A light-emitting device is provided. The light-emitting device includes a first substrate. The light-emitting device also includes a second substrate including a light-shielding structure. The light-emitting device further includes a first light-emitting module and a second light-emitting module being adjacent to each other. The first light-emitting module and the second light-emitting module are disposed between the first substrate and the second substrate. The first light-emitting module and the second light-emitting module are spaced apart by a gap, and the light-shielding structure at least partially covers the gap in a top view direction of the light-emitting device.

Abstract: The present disclosure relates to a display panel and a display device. The display panel includes a display substrate and an encapsulating unit. The encapsulating unit is disposed on the display substrate, and the encapsulating unit includes at least one buffer layer. The buffer layer includes a buffer body and first buffer particles. The buffer body is deformable under an action of an external force thereby compressing the first buffer particles, and the first buffer particles are elastically deformable or capable of being crushed by compression.

Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Abstract: Disclosed is an antenna apparatus including a substrate having a cavity in a first outer surface thereof. The substrate has a sidewall defining a portion of the cavity, and a first edge contact is formed at the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact. An antenna element, disposed at a second outer surface of the substrate opposite the first outer surface, is electrically connected to RF circuitry within the IC chip through a conductive via extending within the substrate.

Abstract: Packaged LEDs with phosphor films, and associated systems and methods are disclosed. A system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond site, an LED carried by the support member and having an LED bond site, and a wire bond electrically connected between the support member bond site and the LED bond site. The system can further include a phosphor film carried by the LED and the support member, the phosphor film being positioned to receive light from the LED at a first wavelength and emit light at a second wavelength different than the first. The phosphor film can be positioned in direct contact with the wire bond at the LED bond site.

Abstract: The present application relates to an encapsulation film, a method for producing the same, an organic electronic device comprising the same, and a method for preparing an organic electronic device using the same, which allows forming a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, and can effectively release heat accumulated inside the organic electronic device and prevent occurrence of bright spots of the organic electronic device.

Abstract: The present technology relates to a solid-state imaging device that includes a sensor substrate having at least a first pixel region and a second pixel region, and a light shielding body substrate which is stacked on an upper surface of the sensor substrate and has a light shielding body surrounding a plurality of light guide paths, in which the plurality of light guide paths includes at least a first light guide path corresponding to the first pixel region, and a second light guide path corresponding to the second pixel region, a plurality of pixels included in the first pixel region has a light shielding structure based on respective pixel positions in the first pixel region, and a plurality of pixels included in the second pixel region has a light shielding structure based on respective pixel positions in the second pixel region.

Abstract: An OLED display panel, a display device and a method for manufacturing the OLED display panel are provided. The display panel includes a display panel body, and an encapsulation layer disposed on the display panel body and applied to encapsulate the display panel body. The encapsulation layer has a gradually increasing thickness in a direction from a central position of the display panel to an edge position of the display panel.

Abstract: Semiconductor device and formation method are provided. The method includes providing a substrate, a first fin and a second fin on the substrate, an isolation structure covering a portion of sidewalls of the first and second fins, a gate structure across the first fin or the second fin, a first doped source/drain region in the first fin, a second doped source/drain region in the second fin, and an interlayer dielectric layer on the isolation structure, the first and second fins, and the gate structure. A first through hole is formed in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region. A second through hole is formed in the interlayer dielectric layer on the isolation structure to connect to the first through hole. A first plug is formed in the first through hole and a second plug is formed in the second through hole.