Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.

Abstract: The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a device under test. Such random accesses may more closely resemble actual accesses to the registers of a device during normal operation, thus providing a more thorough test.

Abstract: This invention provides a semiconductor memory device and its data writing method capable of saving the needed time to a minimum even in repeating a data write operation maximum number of times. More specifically, this invention provides a semiconductor memory device and its data writing method as follows. A flash memory 101 is set at a test mode by fixing the test pad TP at L level. When a verify operation passes, a verify pass signal input terminal (VPASS) of a data write controlling circuit WCC and a verify pass signal input terminal (VPASS) of a data write counter circuit WCT are fixed at L level by a verify pass signal invalidating means 3 although a verify circuit VC outputs an L level verify pass signal VPASS. A latch circuit LC holds a latched verify pass signal VPL at H level and a verify start signal input terminal (VR) of the verify circuit VC is fixed at L level. A write operation without a verify operation is repeated number of times preset in the data write counter circuit WCT.

Abstract: A method and device for comparing two generic digital signals over a wide range of data rates and for counting the number of bit errors between digital signals under the conditions of noise and jamming. The bit error tester of the invention compares the digital signal sent with the digital signal received back from the unit under test and outputs the error signal. In the preferred arrangement of the invention, a field programmable gate array is used and a switch and LED display are used to introduce and monitor a time delay in the sent signal to ensure that the signals are in time alignment prior to comparison.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros includes a memory cell array connected to word lines and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line and outputs defect information to a redundant signal line. The redundant memory macro includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Abstract: A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test target system such as a logic circuit is tested, data of the input circuits is circulated in the BSPC to set the initial state. After a system clock is activated, data of the input circuits is loaded into shift registers provided in the input circuits or data of the output circuits is loaded into shift registers provided in the output circuits. A shift clock is activated to extract the data of the input or output circuits through the BSPC. Enable data is circulated in the BSPC, and data of the output circuits is supplied to the test bus only when the enable data is active.

Abstract: Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.

Abstract: A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having a value identifying a position of a particular edge within the pattern that is to initiate a next assertion of the trigger signal. The triggering circuit asserts the trigger signal when the first and second data values match and de-asserts the trigger signal when the first and second data do not match. In a repetitive mode of operation, the triggering circuit keeps the second data value constant so that it always asserts the trigger signal in response to the same edge of the pattern.

Abstract: A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in each of its branches, thereby producing respective first and second delayed clock signals. A test signal generator generates a plurality of test signals that may simulate memory command or address signal. A multiplexer couples the test signals to first and second inputs of a transmitter in a normal test mode but to only the first input in a special test mode. The transmitter outputs the signal applied to its first input responsive to the first delayed clock signal and it outputs the signal applied to its second input responsive to the second delayed clock signal.

Abstract: A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said memory device is satisfying conditions for performing test, and when an output of the entry circuit is generated and a memory arrangement of the memory device is in a write enable state, a gate circuit generates an output to activate a buffer circuit, by which the internal signal is written to the memory arrangement by being connected to a data write input of the memory arrangement via the buffer circuit, then reading the written data to the outside from the memory arrangement, and performing the measurement related to the internal signal by detecting data change points.

Abstract: A method for providing error compensation to a signal includes providing error adjustment to a signal at a transmitter and communicating the signal over a channel at a channel speed. The method includes receiving the signal from the channel at the channel speed and sampling the signal at a speed less than the channel speed to yield a sampled signal. The method includes determining an error associated with the signal and determining compensation information for providing the error adjustment. The compensation information is based on the error and is determined at a compensation speed. The compensation speed is less than the channel speed. The method also includes communicating information to the transmitter for providing error adjustment. The information communicated to the transmitter may comprise the compensation information. The information communicated to the transmitter may also comprise intermediate information from which the compensation information is determined.

Abstract: The invention relates to a method and device for operating and/or testing memory units, which make it possible to conduct a time-saving test of semiconductor memories during running operation. The inventive method for testing memory units having storage locations provides that, for the storage locations, a first item of test information is formed according to a variable parameter assigned to the respective storage location and according to the contents of the respective storage location.

Abstract: A method of reproducing data by performing error correction on data read from a recording medium. The method includes reading a sync pattern, checking if the sync pattern has been read, recovering data following the sync pattern when the sync pattern has not been read, and performing the error correction on the recovered data. The data following the sync pattern is recovered in the error correction, which makes it easier to lengthen the time width of a detection window setting signal for detecting the sync pattern.

Abstract: When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.