Abstract: A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

Abstract: A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.

Abstract: A destination node in a data network for transmission of real-time data by a data telegram, the data telegram including an identification, data and a transfer status, is provided. The destination node includes a device for receiving a first data telegram, a device for storing the data of the first data telegram and an assigned timer value, a device for receiving a second data telegram and a device for replacing the stored data of the first data telegram, wherein the stored data of the first data telegram is replaced with data of the second data telegram. Further, a method and a non-transitory storage medium are provided.

Abstract: A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard, and received by the interface from a test device, the interface outputs signals corresponding to the test standard to a semiconductor device to be tested. In a second mode of the interface, in reaction to test signals corresponding to the test standard and received by the interface from a test device, the interface outputs signals that do not correspond to the test standard to a semiconductor device to be tested.

Abstract: Standardized scan cell logic is enabled to test board-level and circuit-level AC interfaces built into integrated CMOS circuits by verification of high-speed AC coupled non-CMOS logic level signals driven onto non-CMOS logic level AC coupled interconnects in those circuits.

Abstract: The present invention provides a disc device capable of normally reproducing recorded information on a disc type recording medium while complementing the recorded information in a damaged portion of the recording medium with complementary information, and capable of constantly holding useful complementary information. The complementary information for complementing the recorded information in the damaged portion of the optical disc is acquired from a server and saved in a storage area of a storing unit, and the recorded information on the optical disc is reproduced while complementing the recorded information in the damaged portion with the complementary information.

Abstract: A communication link protocol is provided for communicating between nodes of an interconnect system via a communication link. In one embodiment, the communication link protocol includes a direct memory access (DMA) command for writing a block of data from a local node to a remote node via the communication link; an administrative write command for writing data from a local node to registers in a remote node via the communication link for administrative purposes; a memory copy write command for writing a line of memory from a local node to a remote node via the communication link when any data is written into that line of memory; and a built in self test (BIST) command for testing the functionality of the communication link.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment detect that a first packet is not received, add a place holder for the first packet in a buffer, request retransmission of the first packet, and create an estimated packet based on a combination of a second packet previous to the first packet, a third packet following the first packet, and a fourth packet from a previous frame that is spatially corresponding to the first packet. In another embodiment, a method, apparatus, system, and signal-bearing medium are provided that send a encoded packet to a receiver, save the encoded packet in a bitstream, determine whether the encoded packet is lost, and when the encoded packet is lost, decode the bitstream with the lost packet omitted and insert a reconstructed frame associated with the lost packet into a reference frame storage. In another embodiment, when the encoded packet is lost, a decoder is run on a reference frame chosen as the last uncorrupted frame.

Abstract: When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal lines of one of the integrated circuit devices of the multi-chip integrated circuit package to permit direct testing of the integrated circuit device.

Abstract: Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

Abstract: A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.

Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: A method for evaluating an erroneous state associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are executed using the information in order to identify an erroneous state associated with a sub-space within the target circuit. A path associated with the erroneous state is identified. The path reflects a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered.

Abstract: The invention relates to a method for transmitting real time-critical data using data messages in a data network. The data messages have an identification, useful data and a transfer status. According to the inventive method, data messages comprising errors are replaced by replacement messages that have the same structure as the data messages. The replacement message has the same identification as the data message to be replaced and is thus forwarded via the switching node, which would have been used to route the error-free data message. The replacement message can contain details of the type of transmission error.

Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A pattern correcting device corrects random test patterns generated by pseudo random number pattern generator (PRPG) into test patterns for a test to be input to shift registers. A pattern correcting device corrects the test patterns in unit of specified group, and individually releases correction of the test patterns when the correction in unit of the group is not appropriate. Furthermore, an unknown value mask device masks shift registers that output unknown values based on a control signal, and individually releases a mask of a shift register that outputs a fault value.

Abstract: A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

Abstract: An ECC block is constituted by RS(248, 216, 33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16 bytes, parities of 32 bytes (symbols) are calculated. Only the BCA data of 16 bytes and the parities of the former 16 bytes of the 32-byte parities, that is, a total of 32 bytes only, are recorded in a burst cutting area of an optical disc. In decoding, error correction processing is carried out by using the fixed data of 200 bytes. The unrecorded parities of 16 bytes are processed as having been erased. Thus, the error correction capability in a burst cutting area of an optical disc can be improved.

Abstract: A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.