Abstract: Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop (314) as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the reset condition of the flip flop. In one implementation, the flip-flop is reset when the logic level is different than an expected logic level. In another implementation, a pair of flip-flops (414, 418) are implemented such that only one flip-flop is reset at a particular logic level; if the logic level crosses, both flip-flops are reset. The aforesaid condition of both flip-flops being reset is used to indicate the logic level crossing.

Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Abstract: A method and protocol tester for decoding data for the performance of a measurement task, which data is encoded in accordance with a protocol description, includes modifying the protocol description with respect to the measurement task by compressing protocol elements that are of no relevance to the measurement task and decoding the encoded data according to the modified protocol description to provide only decoded data relevant to the measurement task. The decoded data may be filtered before further processing according to a filter condition determined by the measurement task. Alternatively the filter condition may be installed as part of the modified protocol description. Then additional filtering may be applied when there are further filter conditions determined by the measurement task. The result is a protocol tester that permanently stores the protocol description while allowing modification of the protocol description for each measurement task, reducing storage and calculation requirements.

Abstract: An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

Abstract: A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular embodiment, the method may include selecting to receive the output data from the first register or the second register by use of a control line. In another particular embodiment, the method may include selecting to receive the RAM input data from the first register or the second register by use of a control line. The control line is configured dynamically by hardware or software on cycle by cycle basis. In a particular embodiment, the test is a built-in-self-test (BIST).

Abstract: A method and apparatus for testing an integrated circuit using built-in self-test (BIST) techniques is described. In one aspect, a BIST circuit comprises a scan monitor with hold logic and a signature generation element. The hold logic is operable to suspend signature generation in the signature generation element at any desired point in the test sequence. In some embodiments, the hold logic comprises a scan-loadable signature hold flip-flop which allows the logic BIST controller to be restarted from any selected pattern within a pattern range and to run to any subsequent pattern. The BIST session can be run incrementally, testing and reporting intermediate MISR signatures. External automatic testing equipment can suspend signature generation at selected times during a BIST session to prevent tainting of the signature generation element. The hold logic also may comprise a rotating hold ring to suspend signature generation during predetermined shift cycles.

Abstract: In some embodiments, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical OR operation is applied to each bit in the memory with a bit value as the first operand and a corresponding register value in the first register as the second operand. Additionally, the method includes initializing each bit in the memory to one. Also, a logical AND operation is applied to each bit in the memory with the bit value as the first operand and a corresponding register value as the second operand.

Abstract: A semiconductor device with test interface, as well as to a method for operating a semiconductor device is disclosed. In one embodiment, in a test operating mode, the semiconductor device is, via a first pin, supplied with a work cycle signal synchronized with a test environment and, via at least one second pin, with test data. In accordance with a first embodiment it is suggested, so as to reduce the number of pins, that the work cycle signal is simultaneously used as test data clock signal.

Abstract: An ECC block is constituted by RS(248,216,33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16 bytes, parities of 32 bytes (symbols) are caculated. Only the BCA data of 16 bytes and the parities of the former 16 bytes of the 32-byte parities, that is, a total of 32 bytes only, are recorded in a burst cutting area of an optical disc. In decoding, error correction processing is carried out by using the fixed data of 200 bytes. The unrecorded parities of 16 bytes are processed as having been erased. Thus the error correction capability in a burst cutting area of an optical disc can be improved.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.

Abstract: In an integrated digital circuit, at least one derived data signal is generated from a data signal that is to be transmitted via a line of the digital circuit, by inverting at least two bits of the data signal. The circuit is also provided with an evaluation unit for evaluating the susceptibility of the data signal and the derived data signal, or of derived data signals to interference caused by a capacitive coupling of the line to at least one neighboring line.

Abstract: A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.

Abstract: An apparatus for controlling a Hybrid Automatic Repeat Request (HARQ) is provided. In the apparatus, a physical layer includes a decoder for decoding a control message received over the packet data control channel, a demodulator for demodulating packet data received over the packet data channel, and a turbo decoder for decoding the demodulated packet data. A physical layer's HARQ controller determines whether to demodulate and decode the received packet data depending on a decoding result of the control message, outputs the decoded control message to the demodulator and the turbo decoder for demodulation and decoding of the received packet data, controls output of a response signal according to decoding result of the packet data, and delivers the turbo-decoded packet data to an upper layer.

Abstract: The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying good and bad scan paths among a set of scan paths. A scan path is bad if it is not producing any output. A scan path is good if it is producing a correct output. A clock set is generated for each scan path. The clock set includes all clock elements whose outputs impact the scan path. A union of the scan path clock sets for the bad scan paths is created. Good clock elements are removed from the union. A clock element is presumed to be good if it is associated with a good scan path. Clock elements remaining within the union of clock sets for the bad scan paths are analyzed to determine the source of errors. In one embodiment, multiple input clock elements in all bad scan paths are analyzed first, followed by analysis of single input clock elements in all bad scan paths and followed by analysis of any other clock elements in any of the bad scan paths.

Abstract: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Abstract: A method for correcting data signal errors in a meter has been developed. The method includes receiving ordered data signals from the meter. Next, the sequenced of ordered data signals is analyzed to determine whether a data signal is missing. Finally, if a data signal is missing, a predetermined value is added to a sequence counter to compensate for the missing signal.

Abstract: In accordance with the invention, a Logging Administration Maintenance and Billing Entity (LAMB) is interfaced to a network transport bus for logging network traffic, for error tracking, error replay, and billing functions. In the exemplary embodiment, the LAMB records transactions from a subscriber configuration interface (SCI). Information about SCI transactions may include, for example, time, date, originator information, transaction ID, destination information, message information, SCI functions accessed by the originator, errors, and any other function or process performed by the SCI.

Abstract: A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.

Abstract: The semiconductor test system comprises a test device for testing semiconductor devices including redundant circuits to obtain fail information of defective parts of the semiconductor devices; a redundant remedy judging device which includes fail memories for storing the fail information, and a redundant remedy judging unit for judging based on the fail information stored in the fail memories as to whether or not the redundant remedy replacing the defective parts of the semiconductor devices with the redundant circuits can be made, and which is provided independent of the test device, wherein the test device and the redundant remedy judging device are interconnected with each other via a network, and fail information is transmitted from the test device to the redundant remedy judging device.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.