Abstract: A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.

Abstract: A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.

Abstract: A communications system employs a HARQ method and, for at least some transmission formats, incremental redundancy (IR) signals. For such formats, the multiple IR signals are derived from a single turbo encoded signal by forming multiple permutations of the encoded signal. The permutations are then converted to the coding rate of the selected transmission format. It is demonstrated by simulation that the present proposal achieves a better performance than the known HARQ techniques, while its implementation is simpler. For certain transmission formats, the transmitted signal in response to a retransmission request is identical to the first transmitted signal.

Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.

Abstract: The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.

Abstract: A two-dimensional parity method and system for rotating parity information in a disk array, such as a RAID, to provide multiple disk fault tolerance with reduced write bottlenecks, is presented. The method includes forming a plurality of blocks, each block comprising a plurality of stripes extending across multiple disks, reserving at least one stripe in each block for parity, dividing each block into a plurality of chunks, wherein at least one of the chunks in the block comprises parity information, and shifting the position of each parity chunk in each block to a different disk with respect to the parity chunk in adjacent blocks. The method further includes shifting the position of each parity strip in the at least one stripe in each block to a different disk with respect to the parity chunk in adjacent blocks. A system for translating information in a disk array includes an array controller configured to shift parity chunks and parity strips.

Abstract: An Reed-Solomon encoder and method for block-code encoding by performing a plurality of Galois-Field (GF) multiplication operations utilizing a single GF multiplier. The multiplier generates a set of partial products that are used to calculate all the multiplication operations required for the encoding.

Abstract: Receiving a packet interleaved with an interleave pattern corresponding to the number of times of retransmission, reception apparatus (200) de-interleaves a pilot sequence contained in the packet with de-interleavers (205-1˜205-N). Correlators (206-1˜206-N) performs correlation calculation between the de-interleaved pilot sequence and a pilot pattern held in the reception apparatus. Maximum value detection section (207) detects the maximum correlation value among the correlation values to detect the number of times of retransmission. Decision section (209) controls combination circuit (213) and error detection section (217) based on the number of times of retransmission stored in storage section (208) and on the number of times of retransmission detected at maximum value detection section (207). This allows a decrease in throughput to be prevented from occurring even in a case where a reception side receives a packet which is different from one which is requested by the reception side.

Abstract: A semiconductor memory device is provided which includes: a plurality of memory cells each formed by latch means; gated clock circuits for writing identical data to all of the memory cells in response to a simultaneous writing signal supplied thereto; inverters for inverting data outputted from the memory cells; and selectors for selectively writing the inverted data to the memory cells.

Abstract: In a read out mode, a NAND circuit to which latch data of both bit lines are input provides an L output when potentials of the bit line pair are constantly identical, and provides an H output when the potentials of the bit line pair change, even when the word line rendered active is switched. In a writing mode, the NAND circuit provides an L output. In a reading mode, H is applied to the gate of a first transistor that connects a bit line BL with the NAND circuit. In a writing mode, H is applied to the gate of the first transistor or a second transistor that connects a bit line /BL with the NAND circuit. Potential change occurs at the bit line pair according to an output of the NAND circuit.

Abstract: An address information detecting apparatus in accordance with the present invention is arranged such that a first interpolation address generating section generates a first interpolation address according to a consistent signal supplied from an address comparison section, and a second interpolation address generating section generates a second interpolation address according to an error detection signal supplied from a CRC error detecting section. When a detected address is consistent with at least either of the first and second interpolation addresses and also no error is discovered according to the error detection signal, the detected address is adopted as absolute location information, whereas in situations other than the above, the first interpolation address is adopted as the absolute location information. On this account, even if an address error is mis-detected, the malfunction of the apparatus is prevented and proper recording/reproduction can be carried out.