Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.

Abstract: The present invention discloses a data transmission method and apparatus. The method comprises: segmenting data to be transmitted into information file segments with a length of Tb bits; performing forward error correction (FEC) coding for Tb information bit sequences composed of bits in same positions in a plurality of continuous information file segments to generate Tb check bit sequences, putting each bit of the check bit sequences in the same position in the check file segments as the corresponding information bit sequences; and transmitting each of the information file segments and check file segments according to their order; the number of bits contained in the information bit sequences being less than or equal to the maximum length of Kmax bits of the FEC-coded information bit sequences.

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract: In one embodiment, an LDPC decoder performs a targeted bit adjustment method to recover a valid codeword after the decoder has failed. In a first stage, a post processor initializes the decoder by saturating LLR values output by the decoder during the last (i.e., failed) iteration to a relatively small value. Then, two-bit trials are performed, wherein LLR values corresponding to two bits of the codeword are adjusted in each trial. Decoding is performed with the adjusted values, and if the number of unsatisfied check nodes exceeds a specified threshold, then a second stage is performed. The post processor initializes the decoder by saturating the LLR values output by the decoder during the last (i.e., failed) iteration of the first stage to a relatively small value. The second stage then performs single-bit adjustment trials, wherein one LLR value corresponding to one bit of the codeword is adjusted in each trial.

Abstract: A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals.

Abstract: The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.

Abstract: A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Embodiments of the present invention provide systems, methods, and computer-readable media for modifying frame error rates associated with a mobile device. In embodiments, a mobile device is assigned an initial frame error rate. In response to determining the initial frame error rate does not match a desired frame error rate, a frame error rate modification request is generated. The frame error rate modification request is transmitted to a base station. At the base station, a modified frame error rate that matches the desired frame error rate is associated with the mobile device.

Abstract: In one embodiment, a matrix-vector multiplication (MVM) component generates a product vector based on (i) an input matrix and (ii) an input vector. The MVM component has a permuter, memory, and an XOR gate array. The permuter permutates, for each input sub-vector of the input vector, the input sub-vector based on a set of permutation coefficients to generate a set of permuted input sub-vectors. The memory stores a set of intermediate product sub-vectors corresponding to the product vector. The XOR gate array performs, for each input sub-vector, exclusive disjunction on (i) the set of permuted input sub-vectors and (ii) the set of intermediate product sub-vectors to update the set of intermediate product subvectors, such that all of the intermediate product sub-vectors in the set are updated based on a current input sub-vector before updating any of the intermediate product sub-vectors in the set based on a subsequent input sub-vector.

Abstract: A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Abstract: The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input and a scan clock signal input; wherein: in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is operable to isolate said scan input from said master latch, and said master latch is operable in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation said data input tristateable device is op

Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.

Abstract: An electronic control apparatus comprises a nonvolatile memory, operating means, determining means and retrying means. The nonvolatile memory stores predetermined data and has a memory region which is divided into a plurality of sub-regions. The operating means executes a check operation for each of the sub-regions in order to check whether the data stored in the nonvolatile memory are normal or not. The determining means determines whether the check operation has detected any data errors. The retrying means allows the operating means to retry the check operation for a predetermined number of times for the sub-regions that have been determined to be in data error by the determining means.

Abstract: The present invention provides for a method of forming at least one ARQ PDU from an ARQ service data unit (SDU), the ARQ PDU comprising a header portion and a data portion, and the method including selective addition of a Length Indicator field to the said header portion responsive to the determination of the presence in the PDU of the last bit of an ARQ SDU and if a HARQ PDU is formed of a plurality of ARQ PDUs wherein the last of the ARQ PDUs is arranged not to include an LI within its header if it is found not to be carrying the last bit of the ARQ SDU and LI will be added to all other ARQ PDUs though they are not carrying last bit of ARQ SDU.

Abstract: The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.

Abstract: A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Methods and systems for storing data in a memory system with different levels of redundancy are disclosed. Methods and systems consistent with the present invention provide allow a redundancy level to be associated with received data, wherein associating the redundancy level of the data includes determining a desired level of protection for that data and determining the redundancy level based on the desired level of protection. A zone within a memory system is located that has a redundancy level that matches the redundancy level of the data, and the data is stored in the located zone with the desired redundancy level.

Abstract: A flash memory system includes a memory unit including a main cell that stores main data and a parity cell that stores parity data, and an ECC receiving a codeword including the stored main data and the stored parity data, performing error correction on the codeword by executing an operation on a finite field with respect to the codeword, and an element of the finite field comprising a codeword corresponding to an erased page of the memory unit.