Abstract: A semiconductor device includes a first protection film for covering a first metal wiring. A second protection film is disposed on the first protection film, which is covered with a solder layer. Even if a crack is generated in the second protection film before the solder layer is formed on the second protection film, the crack is restricted from proceeding into the first protection film.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure unit, a transparent, p-side and n-side electrodes. The unit includes n-type semiconductor layer, a light emitting portion provided on a part of the n-type semiconductor layer and p-type semiconductor layer provided on the light emitting portion. The transparent electrode is provided on the p-type semiconductor layer. The p-side electrode is provided on the transparent electrode. The n-side electrode is provided on the n-type semiconductor layer. The transparent electrode has a hole provided between the n-side and p-side electrodes. A width of the hole along an axis perpendicular to an axis from the p-side electrode toward the n-side electrode is longer than widths of the n-side and p-side electrodes. A distance between the hole and the n-side electrode is not longer than a distance between the hole and the p-side electrode.

Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

Abstract: According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

Abstract: One embodiment of the present invention provides a method for fabricating a group III-V nitride structure with an ohmic-contact layer. The method involves fabricating a group III-V nitride structure with a p-type layer. The method further involves depositing an ohmic-contact layer on the p-type layer without first annealing the p-type layer. The method also involves subsequently annealing the p-type layer and the ohmic-contact layer in an annealing chamber at a predetermined temperature for a predetermined period of time, thereby reducing the resistivity of the p-type layer and the ohmic contact in a single annealing process.

Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

Abstract: A display and a method of manufacturing the same, the display including a substrate main body, a first thin film transistor on the substrate main body, the first thin film transistor including a first gate electrode, the first gate electrode including polycrystalline silicon, a first semiconductor layer on the first gate electrode, first source electrode, and a first drain electrode, and a second thin film transistor on the substrate main body, the second thin film transistor including a second semiconductor layer, the second semiconductor layer including polycrystalline silicon and being on a same plane as the first gate electrode, a second gate electrode on the second semiconductor layer, a second source electrode, and a second drain electrode.

Abstract: Embodiments relate to micromachine structures. In one embodiment, a micromachine structure includes a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element includes a FinFET structure having a height and a width, the height being greater than the width.

Abstract: Micropipe-free, single crystal, silicon carbide (SiC) and related methods of manufacture are disclosed. The SiC is grown by placing a source material and seed material on a seed holder in a reaction crucible of the sublimation system, wherein constituent components of the sublimation system including the source material, reaction crucible, and seed holder are substantially free from unintentional impurities. By controlling growth temperature, growth pressure, SiC sublimation flux and composition, and a temperature gradient between the source material and the seed material or the SiC crystal growing on the seed material during the PVT process, micropipe-inducing process instabilities are eliminated and micropipe-free SiC crystal is grown on the seed material.

Abstract: An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

Abstract: A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at least one of Hf and Zr; and a gate electrode provided on the gate insulation film and including a carbonitride which includes at least one of Hf and Zr.

Abstract: A fabricating method of a semiconductor device is provided. Pillars are formed on a substrate. A first oxide layer is continuously formed on upper surfaces and side walls of the pillars by non-conformal liner atomic layer deposition. The first oxide layer continuously covers the pillars and has at least one first opening. The first oxide layer is partially removed to expose the upper surfaces of the pillars, and a first supporting element is formed on the side wall of each of the pillars. The first supporting element is located at a first height on the side wall of the corresponding pillar and surrounds the periphery of the corresponding pillar. The first supporting elements around two adjacent pillars are connected and the first supporting elements around two opposite pillars do not mutually come into contact and have a second opening therebetween.

Abstract: A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs.

Abstract: Provided is a flat panel display apparatus including a sealant which has a small effective width and is able to effectively attach a substrate and an encapsulation substrate. The flat panel display apparatus includes the substrate, a display unit disposed on the substrate, the encapsulation substrate disposed facing the substrate so that the display unit is disposed on inner side of the encapsulation substrate, and the sealant attaching the substrate and the encapsulation substrate, wherein an end surface of the sealant facing the substrate contacts a silicon oxide layer disposed on the substrate.

Abstract: In a hard facing process, a core material is applied to the base material of an article, which may incorporate metal components. An additive is introduced into a molten puddle generated by the hard facing process. The additive functions to increase the wear resistant capabilities of the hard faced article. In one embodiment, the additive comprises mineral particulates, which may consist of diamond granules.

Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

Abstract: A nonvolatile memory device of the present invention includes a substrate (1), first wires (3), first resistance variable elements (5) and lower electrodes (6) of first diode elements which are filled in first through-holes (4), respectively, second wires (11) which cross the first wires 3 perpendicularly to the first wires 3, respectively, and each of which includes a semiconductor layer (7) of a first diode elements, a conductive layer (8) and a semiconductor layer (10) of a second diode elements which are stacked together in this order, second resistance variable elements (16) and upper electrodes (14) of second diode elements which are filled into second through holes (13), respectively, and third wires (17), and the conductive layer (8) of each second wires (11) also serves as the upper electrode of the first diode elements (9) and the lower electrode of the second diode elements (15).

Abstract: The present invention provides a vapor deposition method and a vapor deposition system of film formation systems by which EL materials can be used more efficiently and EL materials having superior uniformity with high throughput rate are formed. According to the present invention, inside a film formation chamber, an evaporation source holder in a rectangular shape in which a plurality of containers sealing evaporation material is moved at a certain pitch to a substrate and the evaporation material is vapor deposited on the substrate. Further, a longitudinal direction of an evaporation source holder in a rectangular shape may be oblique to one side of a substrate, while the evaporation source holder is being moved. Furthermore, it is preferable that a movement direction of an evaporation source holder during vapor deposition be different from a scanning direction of a laser beam while a TFT is formed.