Patents Examined by Steven J. Fulk
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Patent number: 8637965Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.Type: GrantFiled: January 24, 2012Date of Patent: January 28, 2014Assignees: Renesas Electronics Corporation, Hitachi Yonezawa Electronics Co., LtdInventor: Yoshihiko Shimanuki
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Patent number: 8633491Abstract: An etching resist including first and second portions, the first portion being thicker than the second portion, is formed on a metallic layer. Through the etching resist, a semiconductor layer and the metallic layer are patterned by etching so as to form a wiring from the metallic layer and leave the semiconductor layer under the wiring. An electrical test is conducted on the wiring. The second portion is removed while the first portion is left unremoved. Selective etching is performed through the first portion so as to leave the semiconductor layer unetched to pattern the wiring to be divided into drain and source electrodes. A substrate is cut. In patterning the wiring, the wiring is etched to be cut at a position closer to a cutting line of the substrate with respect to the drain and source electrodes, while leaving the semiconductor layer unetched.Type: GrantFiled: August 20, 2010Date of Patent: January 21, 2014Assignee: Panasonic Liquid Crystal Display Co., Ltd.Inventors: Tetsuya Kawamura, Masashi Sato, Yoshiki Watanabe, Hiroaki Iwato, Masafumi Hirata
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Patent number: 8624337Abstract: A resonator body has an inversion gate, an accumulation gate, and a center region. The resonator body also has a source contact coupled to the center region and a drain contact coupled to the center region. The resonator body further has a first dielectric layer coupled between the inversion gate and the center region. The resonator body also has a second dielectric layer coupled between the accumulation gate and the center region. A resonant body transistor is also disclosed. The resonant body transistor has an inversion gate electrode, an accumulation gate electrode, a source electrode, a drain electrode, and a plurality of anchor beams. The resonant body transistor also has a resonator body coupled-to and suspended-from the inversion gate electrode, the accumulation gate electrode, the source electrode, and the drain electrode by the plurality of anchor beams. A resonant body oscillator is also disclosed.Type: GrantFiled: December 11, 2008Date of Patent: January 7, 2014Assignee: Cornell UniversityInventors: Dana Weinstein, Sunil A. Bhave
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Patent number: 8624226Abstract: An organic light emitting device (OLED) is formed by assembling a first substrate and a second substrate. The second substrate includes several sub-pixels. The first substrate includes several transistors electrically connected to each other and, for each subpixel, a first connecting electrode electrically connected to one of the transistors. Each subpixel includes a light-emitting region and a non light-emitting region. A second connecting electrode is formed in the non light-emitting region and electrically connected to the respective first connecting electrode.Type: GrantFiled: April 3, 2007Date of Patent: January 7, 2014Assignee: Chimei Innolux CorporationInventors: Seok-Woon Lee, Sung-Soo Park, Biing-Seng Wu
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Patent number: 8613898Abstract: A composition of matter includes at least one carbon nanotube (CNT) or a graphene type structure having an outer surface, and a plurality of crystalline polymer supramolecular structures that include a conjugated polymer that are non-covalently secured to the outer surface of the CNTs or the graphene type structure. The conjugated polymer can be a conjugated homopolymer or a block copolymer including at least one conjugated block. The supramolecular structures extend outward from the outer surface of the CNTs or graphene type structures.Type: GrantFiled: January 27, 2011Date of Patent: December 24, 2013Assignee: University of Central Florida Research Foundation, Inc.Inventors: Lei Zhai, Jianhua Liu, Jianhua Zou, Anindarupa Chunder
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Patent number: 8611562Abstract: A sound mixing console operative for combining or processing sound signals of a plurality of input channels is described. The sound mixing console (1) comprises a plurality of sound signal input channels (2a, 2b, 2c . . . ), an input channel fader control system (10, 12) having a plurality of input channel faders (16) which can be selectively coupled to respective ones of said plurality of sound signal input channels (2a, 2b, 2c . . . ). A master section (14) has a plurality of control group faders (17) each for collective control of a different selected group of sound signal input channels. Means are provided for coupling the sound signal input channels (36) of one of said selected groups to respective input channel faders (16) thereby to permit individual adjustment of the sound signals of the input channels of said selected group.Type: GrantFiled: March 12, 2007Date of Patent: December 17, 2013Assignee: Red Chip Company Ltd.Inventor: Alex Cooper
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Patent number: 8609476Abstract: The present invention provides a vapor deposition method and a vapor deposition system of film formation systems by which EL materials can be used more efficiently and EL materials having superior uniformity with high throughput rate are formed. According to the present invention, inside a film formation chamber, an evaporation source holder in a rectangular shape in which a plurality of containers sealing evaporation material is moved at a certain pitch to a substrate and the evaporation material is vapor deposited on the substrate. Further, a longitudinal direction of an evaporation source holder in a rectangular shape may be oblique to one side of a substrate, while the evaporation source holder is being moved. Furthermore, it is preferable that a movement direction of an evaporation source holder during vapor deposition be different from a scanning direction of a laser beam while a TFT is formed.Type: GrantFiled: February 15, 2013Date of Patent: December 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara, Masakazu Murakami
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Patent number: 8598673Abstract: A quad photoreceiver includes a low capacitance quad InGaAs p-i-n photodiode structure formed on an InP (100) substrate. The photodiode includes a substrate providing a buffer layer having a metal contact on its bottom portion serving as a common cathode for receiving a bias voltage, and successive layers deposited on its top portion, the first layer being drift layer, the second being an absorption layer, the third being a cap layer divided into four quarter pie shaped sections spaced apart, with metal contacts being deposited on outermost top portions of each section to provide output terminals, the top portions being active regions for detecting light. Four transimpedance amplifiers have input terminals electrically connected to individual output terminals of each p-i-n photodiode.Type: GrantFiled: August 23, 2010Date of Patent: December 3, 2013Assignee: Discovery Semiconductors, Inc.Inventors: Abhay M. Joshi, Shubhashish Datta
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Patent number: 8598626Abstract: Provided is an epitaxial substrate for semiconductor device that is capable of achieving a semiconductor device having high reliability in reverse characteristics of schottky junction. An epitaxial substrate for semiconductor device obtained by forming, on a base substrate, a group of group III nitride layers by lamination such that a (0001) crystal plane of each layer is approximately parallel to a substrate surface includes: a channel layer formed of a first group III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); and a barrier layer formed of a second group III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0), wherein the second group III nitride is a short-range-ordered mixed crystal having a short-range order parameter ? satisfying a range where 0???1.Type: GrantFiled: August 10, 2010Date of Patent: December 3, 2013Assignee: NGK Insulators, Ltd.Inventors: Makoto Miyoshi, Yoshitaka Kuraoka, Shigeaki Sumiya, Mikiya Ichimura, Tomohiko Sugiyama, Mitsuhiro Tanaka
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Patent number: 8598048Abstract: An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.Type: GrantFiled: July 27, 2011Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Kenneth Robert Rhyner, Peter R. Harper
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Patent number: 8592292Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.Type: GrantFiled: September 2, 2010Date of Patent: November 26, 2013Assignee: National Semiconductor CorporationInventors: Sandeep R. Bahl, Jamal Ramdani
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Patent number: 8592275Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.Type: GrantFiled: May 7, 2013Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventor: Yoshiyuki Kawashima
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Patent number: 8587050Abstract: In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles.Type: GrantFiled: March 14, 2012Date of Patent: November 19, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Ryuji Ohba
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Patent number: 8587082Abstract: An imaging device includes: an optical sensor including a light receiving unit capable of forming an object image; a seal material for protecting the light receiving unit of the optical sensor; an intermediate layer formed at least between the light receiving unit and an opposite surface of the seal material facing the light receiving unit; and a control film arranged between the intermediate layer and the opposite surface of the seal material, wherein, in the control film, a cutoff wavelength is shifted to a shortwave side in accordance with an incident angle of light which is obliquely incident on the film.Type: GrantFiled: February 16, 2012Date of Patent: November 19, 2013Assignee: Sony CorporationInventors: Hiroaki Yukawa, Kensaku Maeda, Taizo Takachi, Yasushi Maruyama
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Patent number: 8563983Abstract: The invention provides a display panel and display device enabling easy connection to an external connection component depending on the type of a mounted component, and provides a display device manufacturing method allowing a simple manufacturing process. The display panel of the present invention is a display panel in which a thin film transistor array substrate and an opposed substrate are disposed opposing each other. The thin film transistor array substrate has a first routing wiring that is routed at the outer edge of the substrate, a common transfer section that is formed at a position overlapping with the first routing wiring when the substrate surface is viewed from a normal direction, and a first terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the first routing wiring, at an end portion of the substrate.Type: GrantFiled: April 6, 2010Date of Patent: October 22, 2013Assignee: Sharp Kabushiki KaishaInventors: Yasuhiro Hida, Gen Nagaoka
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Patent number: 8564021Abstract: To suppress adverse affect caused by dopant in a conductive semiconductor layer in a GaN-based device having a structure in which the conductive semiconductor layer is inserted between a substrate and an active layer. In an HEMT device 10, n-GaN (n-type GaN wafer) is used as a substrate 11. A p-type GaN layer (conductive semiconductor layer) 12 is formed on the substrate 11 for the purpose of reducing a leak current and suppressing current collapse, etc. A non-doped AlN layer (semi-insulating semiconductor layer) 13 is formed on the p-type GaN layer 12, and a channel layer (active layer) 14 formed of semi-insulating GaN and an electron supply layer (active layer) 15 formed of n-AlGaN are sequentially formed by the MBE method, MOVPE method, or the like.Type: GrantFiled: August 10, 2010Date of Patent: October 22, 2013Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 8565451Abstract: Under the control of a controller, a DSP supplies audio signals received from a switch circuit to a main zone DAC, subjects the audio signals received from the aforementioned switch circuit (i.e., audio signals for main zone use) to down-mixing processing so that the number of channels matches the number of output terminals assigned to each zone, and respectively supplies the audio signals subjected to down-mixing processing to the respective switch circuits of each zone. Each of the aforementioned switch circuits supplies the audio signals received from the subzone DAC to the respective volume adjustor of each zone.Type: GrantFiled: August 6, 2008Date of Patent: October 22, 2013Assignee: Yamaha CorporationInventors: Masaya Kano, Hironari Kawai, Tatsuya Takahashi, Daigo Sugiura, Hideyuki Suzuki, Kunihiro Kumagai
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Patent number: 8564086Abstract: An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.Type: GrantFiled: March 29, 2013Date of Patent: October 22, 2013Assignee: General Electric CompanyInventors: Wen Li, Jonathan David Short, George Edward Possin
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Patent number: 8564010Abstract: An LED device includes a strip-shaped electrode, a strip-shaped current blocking structure and a plurality of distributed current blocking structures. The current blocking structures are formed of an insulating material such as silicon dioxide. The strip-shaped current blocking structure is located directly underneath the strip-shaped electrode. The plurality of current blocking structures may be disc shaped portions disposed in rows adjacent the strip-shaped current blocking structure. Distribution of the current blocking structures is such that current is prevented from concentrating in regions immediately adjacent the electrode, thereby facilitating uniform current flow into the active layer and facilitating uniform light generation in areas not underneath the electrode. In another aspect, current blocking structures are created by damaging regions of a p-GaN layer to form resistive regions.Type: GrantFiled: August 4, 2011Date of Patent: October 22, 2013Assignee: Toshiba Techno Center Inc.Inventors: Chih-Wei Chuang, Chao-Kun Lin
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Patent number: 8557703Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.Type: GrantFiled: August 12, 2010Date of Patent: October 15, 2013Assignee: STMicroelectronics, Inc.Inventors: Craig J. Rotay, John C. Pritiskutch