Abstract: A technique is disclosed to implement crossfading of audio tracks. In one embodiment, the function describing the fade out of the ending audio track and/or the slope describing the fade in of the beginning audio track may be altered to increase the perceptible overlap of the two tracks. In another embodiment, the duration of the fade out and/or of the fade in may be altered to increase the perceptible overlap of the two tracks. In other embodiments, one or both of the function and/or duration of the fade out and/or fade in effect may be altered to improve the perceptibility of the overlap or the audio tracks.

Abstract: The present invention provides embodiments of a musical instrument preamplifier. It is especially suited to acoustic and electric guitars and basses. All components, including the power source, are contained within or on the body of the instrument. The preamplifier dubbed BPTD (for Battery Powered Tube Driver) contains a vacuum tube input stage and may utilize a second stage consisting of either a vacuum tube or semiconductor device, such as a JFET. Circuitry is included to bias the cathode heater and the preamplifier circuit with no dangerous high voltages present. The tube may be mounted on the instrument body to provide for a pleasing display.

Abstract: The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure.

Abstract: A channel stop is provided for a semiconductor device that includes at least one active region. The channel stop is configured to surround the semiconductor device, to abut the at least one active region at a periphery of the semiconductor device, and to share an electrical connection with the at least one active region.

Abstract: A semiconductor device includes: a semiconductor substrate; an element isolation insulator; an insulating block; an interlayer insulating film; and a contact. A plurality of active areas extending in one direction and protruding upward are formed at an upper surface of the substrate. The insulating block is disposed directly on the element isolation insulator. The contact is formed in the interlayer insulating film. A lower end of the contact is connected to an upper surface of the active area. A part of a lower surface of the contact located directly on the insulating block is positioned higher than a part of a lower surface of the contact located directly on the active area.

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract: Provided is a semiconductor device which is capable of preventing an increase in power consumption of an SGT, i.e., a three-dimensional semiconductor transistor, due to an increase in off-leak current. The semiconductor device comprises: a first-conductive type first silicon pillar: a first dielectric surrounding a side surface of the first silicon pillar; a gate surrounding the dielectric; a second silicon pillar provided underneath the first silicon pillar; and a third silicon pillar provided on a top of the first silicon pillar. The second silicon pillar has a second-conductive type high-concentration impurity region formed in a surface thereof except at least a part of a contact surface region with the first silicon pillar, and a first-conductive type impurity region formed therein and surrounded by the second-conductive type high-concentration impurity region.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

Abstract: An optoelectronic component (10) comprising at least one metal body (15) and a layer sequence (17), which is applied on a base body (11) and which is embodied to emit an electromagnetic radiation and to which an insulation (12) is applied on at least one side area, wherein the at least one metal body (15) is applied to at least one region of the insulation (12) and is embodied in such a way that it is in thermally conductive contact with the base body (11).

Abstract: A leadframe enhancing molding compound bondability includes a chip base and a pin holder. The chip bases includes a chip pad and a support, wherein the chip pad includes a side protrusion extending out of the support, and the side protrusion has a lower surface, and the support has a sidewall, and wherein the lower surface and the sidewall interconnect at an intersection line, and the lower surface is formed upwardly with a recess. Further, a pin holder includes a pin stand and a seat, wherein the pin stand has an edge portion extending out of the seat, the edge portion has a lower surface, the seat has a sidewall, and the lower surface and the sidewall interconnect at a crossing line. The lower surface of the pin stand is formed upward with a recess. As such, the bondability between the leadframe and the molding compound can be greatly enhanced.

Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material in operation in an electronic device or electronic circuit can be modified/enhanced when subjected to dynamic or stationary magnetic fields with current flowing through the electronic material. Heating or cooling of the electronic material further enhances the electronic properties.

Abstract: Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F).

Abstract: An OLED display including a substrate main body; a first gate electrode and a second semiconductor layer; a gate insulating layer on the first gate electrode and the second semiconductor layer; a first semiconductor layer and a second gate electrode overlying the first gate electrode and the second semiconductor layer, respectively; etching stopper layers contacting portions of the first semiconductor layer; an interlayer insulating layer on the first semiconductor layer and the second gate electrode and including contact holes exposing the plurality of etching stopper layers, respectively; a first source electrode and a first drain electrode on the interlayer insulating layer and the contact holes being indirectly connected to the first semiconductor layer via the etching stopper layers or directly connected to the first semiconductor layer; and a second source electrode and a second drain electrode on the interlayer insulating layer being connected to the second semiconductor layer.

Abstract: A semiconductor device includes an active region including a surface region and a first recess formed below the surface region, the active region extending along a first direction; a device isolation structure provided on an edge of the active region; a gate line traversing over the surface region of the active region along a second direction orthogonal to the first direction; a second recess formed in the device isolation structure to receive a given portion of the gate line into the second recess; a first junction region formed in the active region beneath the first recess and on a first side of the gate line; and a second junction region formed on a second side of the gate line and above the first junction region. The first and second junction regions define a vertical-type channel that extends along lateral and vertical directions.

Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Abstract: A semiconductor package is disclosed. In one aspect, the package includes a base frame and a wiring substrate mounted on the base frame. The base frame has two pieces made of a material with respectively a first and a second coefficient of thermal expansion and connected to each other via resilient connecting structures. The wiring substrate has electric wiring tracks providing the electric connection between first and second bond pads, provided for being electrically connected to bond pads on respectively a die and a printed wiring board. The electrical wiring tracks have flexible parts provided to expand and contract along with the resilient connecting structures.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: A light-emitting diode device is described, which includes a luminous body and a colloid. The luminous body has a light-emitting surface and a bottom surface on opposite sides. The luminous body has a first length, a first width and a beam angle. The colloid covers the luminous body. The colloid includes a first surface and a second surface on opposite sides. The second surface has a second length and a second width. The colloid has a refractive index. A distance between the light-emitting surface of the luminous body and the second surface of the colloid is smaller than a first value and greater than a second value. The first value < the ? ? second ? ? width - the ? ? first ? ? width 2 · cot ? ? ? . The second value < the ? ? second ? ? width - the ? ? first ? ? width 2 · cot ? ? v . The sin ?=1/the refractive index of the colloid, and the ? is a full width at half maximum of the beam angle.

Abstract: A micro movable device according to an embodiment of the present invention may include a signal line formed on a support substrate, a ground line formed on the support substrate and arranged side by side with the signal line, a first driving electrode formed above the signal line, a second driving electrode formed above the ground line, a first auxiliary driving electrode arranged side by side with the first driving electrode, a second auxiliary driving electrode arranged side by side with the second driving electrode, and a movable electrode which is formed above the first driving electrode, the second driving electrode, the first auxiliary driving electrode and the second auxiliary driving electrode with a space therebetween, and which is supported on the support substrate.