Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Abstract: A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; subjecting at least the channel region to a cleaning treatment step; and depositing organic semiconductive material from solution into the channel region by inkjet printing.

Abstract: Device for connecting nano-objects to external electrical systems, and method for producing the device. According to the invention, which applies in particular to molecular characterization, a device including the following is produced: an upper layer equipped with upper contact pads to be connected to a nano-object; a lower layer, equipped with lower contact pads to be connected to an external electrical system; above the lower layer, a bonding layer including electrical through-vias in contact with the lower pads; and, between the bonding layer and the upper layer, at least two layers equipped with conductive lines and electrical vias, for connecting the upper pads to the lower pads.

Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

Abstract: A MEMS component includes a substrate in which at least one cavity is present. The cavity is closed off toward an active side of the substrate. An inactive side is arranged opposite the active side of the substrate, and the substrate is covered with a covering film on the inactive side.

Abstract: An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.

Abstract: The invention provides advances in the arts with useful and novel integrated packaging having inductor elements and adjacent magnetic material enhancing the inductance characteristics of the packaged inductor. Preferably the integrated packages also contain one or more ICs operable coupled to the inductor(s).

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor layer including first and second regions, a pixel portion provided in the first region, electrodes provided in the second region and configured to penetrate the semiconductor layer, and a guard ring provided in the second region and configured to penetrate the semiconductor layer and electrically isolate the pixel portion from the electrodes. An upper surface of the semiconductor layer in the second region is lower than an upper surface of the semiconductor layer in the first region.

Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure disposed under an insulating layer having a plurality of holes. A first electrode is disposed on the insulating layer and a second electrode disposed is disposed under the light emitting structure. A conductive supporting member is disposed under the second electrode. The plurality of contact protrusions are disposed in the holes of the insulating layer and include filler connected to the first conductive semiconductor layer and disposed in the plurality of holes. The conductive supporting member physically contacts with the second electrode and has a thickness thicker than that of the insulating layer. The first electrode is located at a higher position than an entire region of the insulating layer and the insulating layer is located at a higher position than an entire region of the light emitting structure.

Abstract: A light-emitting device comprising a light-emitting layer and a light exit layer. In this case, the light exit layer has a multiplicity of mutually parallel first areas, arranged in an inclined fashion with respect to the light-emitting layer. The light exit layer furthermore has a multiplicity of mutually parallel second areas arranged in an inclined fashion with respect to the light-emitting layer and in an inclined fashion with respect to the first areas. The first areas are transparent and the second areas are reflective to light emitted by the light-emitting layer.

Abstract: A semiconductor device in which an adhesion between a lead and a sealing body (mold sealing body) is improved to prevent the peering is provided. In a semiconductor device having a semiconductor chip, a plurality of leads electrically connected to the semiconductor chip and mainly made of metal and a sealing body for sealing the semiconductor chip, in order to improve the adhesion between the lead and the sealing body (mold sealing body), a material combination with good lattice matching is used as a combination of a surface material of the lead and a material of the sealing body, and the sealing body mainly made of acene is used.

Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely.

Abstract: An electromechanical transducer includes multiple elements each including at least one cellular structure, the cellular structure including: a semiconductor substrate, a semiconductor diaphragm, and a supporting portion for supporting the diaphragm so that a gap is formed between one surface of the substrate and the diaphragm. The elements are separated from one another at separating locations of a semiconductor film including the diaphragm. Each of the elements includes in a through hole passing through a first insulating layer including the supporting portion and the semiconductor substrate: a conductor which is connected to the semiconductor film including the diaphragm; and a second insulating layer for insulating the conductor from the semiconductor substrate.

Abstract: A light emitting device is disclosed. In the light emitting device, the structure of a barrier layer of an active layer is changed, and a band gap energy of an intermediate layer is varied, thereby improving hole injection efficiency of the active layer and thus light emission efficiency.

Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.

Abstract: A thermal detector includes a substrate, a thermal detection element and a support member. The substrate has a recess part with a bottom surface of the recess part being a curved light-reflecting surface. The thermal detection element has a light-absorbing film. The support member supports the thermal detection element. The substrate and the support member are arranged to form a hollow part therebetween. The support member includes a light-absorbing part in which impurities are dispersed in polycrystalline silicon with the light-absorbing part being arranged in at least a part of a surface of the support member facing toward the hollow part so that the light-absorbing part being irradiated by light.