Patents Examined by Steven J. Fulk
  • Patent number: 8754482
    Abstract: A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: June 17, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qiuxia Xu, Dapeng Chen
  • Patent number: 8749001
    Abstract: An electronic component includes: a semiconductor element including a circuit; a vibration element; a first electrode arranged on a first surface of the semiconductor element and connected to the circuit and the vibration element arranged on the first surface side; a second electrode arranged on the first surface; a first wiring board including a first wire connected to the second electrode; and a second wiring board including a second wire to which the first wire is connected. At least a part of an inner side region of an outer contour of the vibration element is arranged to overlap the second electrode in plan view facing the first surface.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: June 10, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Terunao Hanaoka, Akinori Shindo, Yasuo Yamasaki, Seiichi Chiba, Toshiyuki Enta, Shuji Kojima
  • Patent number: 8741722
    Abstract: A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul C. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 8742527
    Abstract: According to one embodiment, a solid state imaging device includes a sensor substrate curved such that an upper face having a plurality of pixels formed is recessed and an imaging lens provided on the upper face side.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Suzuki, Risako Ueno, Honam Kwon, Mitsuyoshi Kobayashi, Hideyuki Funaki
  • Patent number: 8736067
    Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
  • Patent number: 8735197
    Abstract: This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: May 27, 2014
    Assignee: Epistar Corporation
    Inventors: Chin-San Tao, Tzu-Chien Hsu, Tsen-Kuei Wang
  • Patent number: 8735200
    Abstract: Embodiments of the invention provide robust electrothermal MEMS with fast thermal response. In one embodiment, an electrothermal bimorph actuator is fabricated using aluminum as one bimorph layer and tungsten as the second bimorph layer. The heating element can be the aluminum or the tungsten, or a combination of aluminum and tungsten, thereby providing a resistive heater and reducing deposition steps. Polyimide can be used for thermal isolation of the bimorph actuator and the substrate. For MEMS micromirror designs, the polyimide can also be used for thermal isolation between the bimorph actuator and the micromirror.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 27, 2014
    Inventors: Sagnik Pal, Huikai Xie
  • Patent number: 8728850
    Abstract: A method of manufacturing a photodetector structure is provided. The method includes forming a structural layer by making a trench in a bulk silicon substrate and filling the trench with a cladding material, forming a single-crystallized silicon layer on the structural layer, and forming a germanium layer on the single-crystallized silicon layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Chul Ji, Kyoung Won Na, Kyoung Ho Ha, Pil-Kyu Kang
  • Patent number: 8729795
    Abstract: Color purity of a light emitting element is improved without an adverse effect such as reduction in voltage and luminance efficiency. The light emitting element has a light emitting laminated body including a light emitting layer between a pair of electrodes. A buffer layer is provided to be in contact with at least one of the electrodes. One of the electrodes is an electrode having high reflectance and the other is a translucent electrode. By employing a translucent electrode, light can be transmitted and reflected. An optical distance between the electrodes is adjusted in accordance with a thickness of the buffer layer, and accordingly, light can be resonated between the electrodes. The buffer layer is made of a composite material including an organic compound and a metal compound; therefore, voltage and luminance efficiency of the light emitting element is not affected even if a distance between the electrodes becomes long.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryoji Nomura, Satoshi Seo, Yuji Iwaki, Nozomu Sugisawa
  • Patent number: 8723307
    Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Yong Poo Chia
  • Patent number: 8723231
    Abstract: A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 13, 2014
    Assignee: Nvidia Corporation
    Inventor: Michael B. Diamond
  • Patent number: 8722508
    Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
  • Patent number: 8716846
    Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinzhong Yao, Wai Yew Lo, Lan Chu Tan, Xuesong Xu
  • Patent number: 8716836
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: May 6, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata, Taketsugu Yamamoto, Kazumi Wada
  • Patent number: 8716749
    Abstract: Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Hyun-gi Hong, Young-jo Tak, Jae-won Lee, Hyung-su Jeong
  • Patent number: 8716729
    Abstract: A lighting device (1) comprises at least one element (2) emitting light which is at least in part visible, and at least one conversion medium (3), which converts at least part of the radiation emitted by the element (2) into radiation of another frequency. In addition, the lighting device (1) comprises at least one filter medium (4) which filters at least part of the radiation, and which is configured such that the quantity of the conversion medium (4) to be used is reduced for at least one predetermined color saturation and/or one predetermined hue. This means that, compared with a light source corresponding to the lighting device (1) apart from the filter medium (4), savings are made in conversion medium (3) while achieving the same color saturation or the same hue. Light of a predetermined color saturation or of a predetermined hue may be efficiently generated by such a lighting device (1) and the lighting device (1) may be inexpensively produced.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 6, 2014
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Burkard Wiesmann, Herbert Brunner, Joerg Strauss, Julius Muschaweck, Kirstin Petersen
  • Patent number: 8716054
    Abstract: A method for fabricating an image sensor having a pixel region and a logic region, which includes one of: (1) forming a photodiode in a substrate at the pixel region, (2) forming a first interlayer insulating layer on the substrate, (3) forming a first stop film on the first interlayer insulating layer, (4) forming an insulating film on the first stop film, (5) forming a second stop film on the insulating film, (6) forming at least one trench by selective etching of the second stop film and the insulating film positioned at the pixel region for exposing the first stop film, (7) forming conductive material on the second stop film to fill the at least one trench, and (8) forming a zero wiring layer in the at least one trench by planarizing the conductive material until the second stop film is exposed.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 6, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seong Hun Jeong
  • Patent number: 8704275
    Abstract: A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 22, 2014
    Assignee: Nvidia Corporation
    Inventor: Michael B. Diamond
  • Patent number: 8703583
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Patent number: 8698226
    Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: April 15, 2014
    Assignee: University of Connecticut
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos