Abstract: The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A bias circuit includes a current sensor, a transistor, and a low pass filter circuit. The current sensor has a first terminal coupled to a voltage terminal, and a second terminal. The transistor has a first terminal coupled to the second terminal of the current sensor, a second terminal coupled to a radio frequency signal path for providing a bias signal, and a control terminal for receiving a reference voltage. The low pass filter circuit is coupled between the second terminal of the current sensor and the control terminal of the transistor.

Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.

Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.

Abstract: This disclosure describes techniques for compensating for amplifier drift. An amplifier is configured to generate an output that triggers a charge counter to generate a charge count value based on a charge count signal. A current digital-to-analog converter (IDAC) is coupled to the amplifier and configured to provide an offset current to a first input of the amplifier. An offset correction circuit is configured to: determine whether a duty cycle associated with the amplifier exceeds a specified threshold and generate a signal to cause the MAC to adjust the value of the offset current to compensate for amplifier drift based on determining whether the duty cycle exceeds the specified threshold.

Abstract: A signal coupling method and apparatus is disclosed. A coupling network is coupled to convey signals from first functional circuit block to a second functional circuit block. The coupling network includes a first signal path having a first capacitor for providing AC coupling between the first and second functional circuit blocks. The coupling network further includes a second signal path in parallel with the first signal path. The second signal path includes a switched capacitor circuit coupled to receive a first common mode voltage corresponding to the first functional circuit block and a second common mode voltage corresponding to the second functional circuit block.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

Abstract: A semiconductor device includes a semiconductor substrate including a principal surface parallel to a plane defined by a first direction and a second direction substantially orthogonal to the first direction, and the principal surface having a first side parallel to the first direction; first unit transistors, each amplifying a first signal in a first frequency band to output a second signal; and second unit transistors, each amplifying the second signal to output a third signal and aligned in the second direction between the first side and a substrate center line in the first direction in plan view of the principal surface. A first center line in the first direction of a region in which the first unit transistors are aligned is farther from the first side than a second center line in the first direction of a region in which the second unit transistors are aligned.

Abstract: Bias networks for amplifiers are disclosed. An example bias network includes an adaptive bias circuit, configured to generate a bias signal for an amplifier, and further includes a coupling circuit, configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is made adaptive in that its' impedance depends on a power level of an input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit may adapt to the input power level and, thereby, may modify the bias signal to reduce/optimize at least some of the nonlinearity that may be introduced to the bias signal by the adaptive bias circuit.

Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.

Abstract: A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180°×N?90° where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180°×M?180° where M is a positive integer.

Abstract: A method for calculating a calibration gain used for common-mode rejection in a current sensing system may include measuring a first value of a common-mode voltage associated with the current sensing system and a first output value of the current sensing system occurring at the first value of the common-mode voltage, measuring a second value of the common-mode voltage associated with the current sensing system and a second output value of the current sensing system occurring at the second value of the common-mode voltage, and based on a difference between the second output value of the current sensing system and the first output value of the current sensing system and a difference between the second value of the common-mode voltage and the first value of the common-mode voltage, calculating the calibration gain.

Abstract: Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential, a non-inverting input node receiving the input signal, and an output node connected to the second signal line; a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.

Abstract: An amplifier, comprising: an amplifying element having an input side and an output side; a first transformer on the output side of the amplifying element arranged to mutually couple a fraction of the output current from the amplifying element onto the input side of the amplifying element; a second transformer on the input side of the amplifying element arranged to increase the input voltage on the input side via mutual coupling of its primary and secondary windings; wherein a primary winding of the first transformer is connected to an output of the amplifying element; wherein a secondary winding of the first transformer is ac connected to a secondary winding of the second transformer; and wherein the primary winding of the first transformer is dc blocked from the secondary winding of the second transformer. The negative and the positive reactive feedback loops are not formed from the same trifilar transformer.

Abstract: Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.

Abstract: A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.

Abstract: An amplifier applied to TIA is provided to suppress the noise caused by a current source. An amplifier constituting a transimpedance amplifier includes an inductor element inserted between a current source connected to an input terminal of an amplification stage and a power source voltage line. The current source includes a first transistor in which a base terminal is connected to a current control bias and a collector terminal is connected to the input terminal. The inductor element is inserted between the emitter terminal of the first transistor and the power source voltage line.

Abstract: Aspects of this disclosure relate to an impedance transformation circuit for use in an amplifier, such as a low noise amplifier. The impedance transformation circuit includes a matching circuit including a first inductor. The impedance transformation circuit also includes a second inductor. The first and second inductors are magnetically coupled to each other to provide negative feedback to linearize the amplifier.