Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures.

Abstract: A semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view and having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel with each other in a first horizontal direction, each including a bit line; a plurality of buried contacts filling lower portions of spaces among the plurality of bit line structures on the substrate; a plurality of landing pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being at the same level as the plurality of landing pads.

Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.

Abstract: The present disclosure provides a manufacturing method of a memory structure. The manufacturing method includes the operations of: receiving a substrate; forming a landing pad layer in the substrate; forming trenches over the landing pad layer; and forming a top pad over the trenches to form the capacitor array. The operation of forming the trenches over the landing pad layer includes the operations of: forming an integrated layer having an array pattern over the landing pad layer; forming, by a chop mask, a masking layer to mask an edge portion of the array pattern so as to define a rectangle portion of the array pattern; and etching the integrated layer according to the rectangle portion of the array pattern to form the plurality of trenches. The edge portion of the array pattern surrounds the rectangle portion of the array pattern.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductive layer and a metal layer. The first conductive layer is located on the first electrode. The metal layer is located on the first conductive layer. The metal layer exposes a portion of the first conductive layer. The insulating layer is located between the first electrode and the second electrode.

Abstract: According to one embodiment, a semiconductor device including, a panel including an inorganic film, and a first pad and a second pad positioned on the inorganic film, and a line substrate including a first connection line electrically connected to the first pad, and a second connection line electrically connected to the second pad, the line substrate positioned on the panel, wherein the inorganic film includes a first cut portion overlapping the first connection line, a second cut portion overlapping the second connection line, and a first extension portion between the first cut portion and the second cut portion, and the first cut portion, the second cut portion, and the first extension portion extend to a first side of the panel.

Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

Abstract: An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary circuit includes a first terminal which is coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal which is coupled to the pad, the ESD primary circuit and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type having a first terminal coupled to the first terminal of the pull-down circuit. A breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary circuit.

Abstract: A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure.

Abstract: One illustrative photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, the N-doped waveguide structure comprising a plurality of first fins, and a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. In this example, the photodetector also includes at least one N-doped contact region positioned in the semiconductor material and a P-doped contact region positioned in the detector structure.

Abstract: A memory device and a method of fabricating the memory device are disclosed, in which a plurality of contacts are formed on a substrate, and voids are formed in the contacts. The contacts are electrically isolated from one another by cutouts directly connecting with the voids. Insulating layers at least fill the cutouts. Since the cutouts are connected with the voids and the insulating layers fill at least the cutouts, the voids can be kept at least partially void. Thus, they can reduce parasitic capacitance between the contacts, prevent the degradation of data retention properties of the memory device, and overcome the problem of malfunctioning. Additionally, the need to avoid the formation of voids in the contacts by imposing strict requirements on the process for forming the contacts can be dispensed with, thus widening the process window for the formation of the contacts.

Abstract: A software-based (“soft”) real-time hub designed and implemented for use in simulation (or control testing) systems such as to provide a modular soft-real-time PIL. A simulation system of the present description typically may include one or more of the following useful subsystems or components: (a) a soft-real-time hub; (b) simulation interfaces; and (c) hardware emulation subsystems/devices. The soft-real-time hub is typically a combination of hardware and software adapted to provide deterministic data transport between simulations and input/output (I/O) emulation. By creating a common point, the hub enables simulation modules to be swapped out as the simulation system progresses without the operator having to worry about interface timing, forcing, or data visualization. A desirable aspect of the simulation system is it allows for testing certain conditions by forcing I/O and then seeing how the controller or system under testing responds.

Abstract: Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

Abstract: A capacitor includes: a semiconductor substrate including at least one substrate trench group; at least one laminated structure, each laminated structure includes n conductive layers and m dielectric layers, the first conductive layer in the n conductive layers is disposed above the semiconductor substrate and in the substrate trench group, the i-th conductive layer in the n conductive layers is provided with the i-th conductive layer trench group, and the (i+1)th conductive layer in the n conductive layers is disposed above the i-th conductive layer and in the i-th conductive layer trench group, where m, n, and i are positive integers, and n?2, 1?i?n?1; a first external electrode connected to some conductive layers; and a second external electrode connected to other conductive layers.

Abstract: The present invention discloses a saw-toothed electrode and a method for enhancing the performance of a nanowire UV detector, and relates to the field of semiconductor technologies. The saw-toothed electrode includes two symmetrically arranged patterns; the pattern includes a rectangle and multiple isosceles trapeziums; lower bases of the isosceles trapeziums are connected to a same long side of the rectangle; opposite sides of the two patterns are sides on which multiple isosceles trapeziums are located; equal-length legs and the upper base of the isosceles trapezium are used to grow nanowires; and nanowires grown on upper bases of two isosceles trapeziums, symmetric to each other, on the opposite sides of the two patterns form bridges.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, and a capacitor structure is provided. The bit line structure is located on the substrate. The contact structure is located on the substrate on one side of the bit line structure. The capacitor structure is located on the contact structure. The capacitor structure includes a first electrode, a second electrode, and an insulating layer. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is only located on a part of the contact structure. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode.

Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.