Abstract: Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and thin-film transistors disposed on the base substrate, where the thin-film transistors each comprises a gate, an active layer insulated from the gate, and two ohmic contact parts in direct contact with the active layer, leaving a gap region between the two ohmic contact parts; and each of the ohmic contact parts comprises a lightly doped region and a heavily doped region, and an orthographic projection of the lightly doped region on the base substrate and an orthographic projection of the heavily doped region on the base substrate do not overlap each other.

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

Abstract: In a graphene-semiconductor heterojunction photodetector and a method of manufacturing the same according to the present inventive concept, a source electrode and a test electrode are formed to face each other on a graphene layer, and a drain electrode is formed in a direction perpendicular to a central region portion of the graphene layer, so that the drain electrode may be physically separated from the graphene layer. Further, charges formed at the central region portion of the graphene layer are transmitted to the drain electrode through a substrate, so that high photosensitivity may be secured, and a high output voltage may be secured for the applied light. Accordingly, the drain electrode is formed at a side surface of the graphene layer, so that the size of the drain electrode may be easily controlled, and a high output voltage may be obtained.

Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a source/drain structure formed adjacent to the gate structure in the substrate and a contact formed over the source/drain structure. The semiconductor structure further includes a metal-containing layer formed over the contact and a dielectric layer covering the gate structure and the metal-containing layer. The semiconductor structure further includes a first conductive structure formed through dielectric layer and the metal-containing layer and landing on the contact. In addition, a bottom surface of the metal-containing layer is higher than a top surface of the gate structure.

Abstract: An array substrate of the present invention includes: a first metal layer; an insulating layer on the first metal layer; an amorphous silicon layer on a surface of the insulating layer away from the first metal layer; an amorphous silicon doped layer arranged on a surface of the amorphous silicon layer away from the insulating layer; a second metal layer including a first portion and a second portion, the first portion arranged on a surface of the amorphous silicon doped layer away from the amorphous silicon layer, a second portion arranged on the first surface and in contact with the first metal layer; a protective layer arranged on the first metal layer and the second metal layer; a first transparent electrode connected to the first metal layer through the protective layer; and a second transparent electrode connected to the second metal layer through the protective layer.

Abstract: In modeling contact between two or more objects (such as a robotic arm placing a block on a stack of blocks) or articulations of a series of linked joints (such as modeling a backhoe), current techniques can introduce additional energy into the system or fail to resolve a constraint imposed on the system. The current techniques attempt to resolve these issues, for example, by using very small time steps. Very small time steps, however, can significantly increase computational costs of the modeling simulation. The disclosed simulation system for rigid bodies uses a time interval to reduce linearization artifacts due to the small time steps and reduce computational costs with faster solver convergence by permitting more efficient bias calculations. High mass handling can also be improved through the more efficient bias calculations.

Abstract: Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

Abstract: A light-emitting device includes a substrate including a base member having an upper surface having a substantially rectangular shape, a lower surface opposite to the upper surface, a first longer lateral surface, a second longer lateral surface opposite to the first longer lateral surface, a first shorter lateral surface, and a second shorter lateral surface opposite to the first shorter lateral surface, first wirings disposed on the upper surface, and second wirings disposed on the lower surface and each electrically connected with a respective one of the first wirings; at least one light-emitting element; and a light-reflective covering member covering lateral surfaces of the light-emitting element and the upper surface of the base member. The base member has at least one first recess open at the upper surface and the first longer lateral surface. Surfaces defining the at least one first recess are covered with the covering member.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: A conductive pattern and a method for manufacturing the same, a thin film transistor, a display substrate and a display device are provided. The method includes: step A, forming a metal layer on a base substrate; step B, forming a first conductive buffer layer on the metal layer; step C, patterning the metal layer and the first conductive buffer layer to form a conductive sub-pattern; and performing steps A to C repeatedly for N times to form N conductive sub-patterns that are stacked on the base substrate. The conductive pattern comprises the N conductive sub-patterns, and N is a positive integer greater than 1.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a transistor disposed within the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; and a capacitor disposed within the second dielectric layer and electrically connected to the transistor, wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer. Further, a method of manufacturing a semiconductor structure includes disposing an electrostrictive material over a first electrode layer; disposing a ferroelectric material over the first electrode layer; removing a portion of the ferroelectric material to form the ferroelectric material; and removing a portion of the electrostrictive material to form the electrostrictive layer.

Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a first switching element, a second switching element, and a conductor. The conductor is provided at least in part on the first semiconductor layer and located between the first switching element and the second switching element in a first direction.

Abstract: The present invention provides a display panel and a manufacturing method thereof. The display panel includes a common electrode layer, a pixel definition layer, a light emitting layer, a transparent pixel electrode layer, and an electrode connecting layer which are sequentially stacked. An electrode connecting portion is formed on the electrode connecting layer and electrically connected with the transparent pixel electrode layer and a signal electrode. Because a common electrode is disposed in a light emitting direction away from the light emitting layer, a light transmittance is not required.

Abstract: An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.

Abstract: An integrated circuit package with a buffer providing radiation protection to memory elements and components is described. The integrated circuit packages and the incorporated buffers provide a protective distance between potential sources of internal radiation particles within the integrated circuit package and any memory elements/components which may be sensitive to radiation such as alpha particles. This protective distance allows for the integrated circuit packages to be completed or assembled without needing added more expensive or redundant memory components.