Abstract: A display substrate includes a plurality of pixel units. Each of the plurality of pixel units is provided with a plurality of sub-pixels. Each of the plurality of sub-pixels is correspondingly provided with a thin film transistor TFT. At least two TFTs are symmetrical about a geometric center point of the pixel unit.

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

Abstract: A method includes positioning an integrated circuit package in a coining apparatus having a fixture and a pressing plate. The integrated circuit package includes a substrate, an integrated circuit device disposed on a top surface of the substrate, and a plurality of solder balls disposed on a bottom surface of the integrated circuit package. The fixture includes a support structure and a cavity. The cavity receives the integrated circuit device while the support structure supports portions of a top surface of the integrated circuit package. The pressing plate is pressed against two or more of the solder balls, coining the two or more solder balls until each solder ball has a desired coined surface profile.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. The 3D memory device can include a structure of a plurality of gate electrodes insulated by a sealing structure over a substrate. The sealing structure can include an airgap between adjacent gate electrodes along a direction perpendicular to a top surface of the substrate. The 3D memory device can also include a semiconductor channel extending from a top surface of the structure to the substrate. The semiconductor channel can include a memory layer that has two portions extending along different directions. The 3D memory device can further include a source structure extending from the top surface of the structure to the substrate and between adjacent gate electrodes along a direction parallel to the top surface the substrate.

Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: The preset disclosure provides a display panel and a display device. The display panel includes: a first substrate; a first bonding electrode which is located on a first surface of the first substrate facing a light-outgoing direction of the display panel and is located at an edge outside a display area of the display panel.

Abstract: A semiconductor substrate includes first and second main surfaces opposing each other. The semiconductor substrate includes second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. The second semiconductor regions are two-dimensionally distributed in a first direction and a second direction orthogonal to each other when viewed in a direction orthogonal to the semiconductor substrate. The first region and the second region are adjacent to each other in a direction crossing the first direction and the second direction. The textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.

Abstract: The present disclosure relates to an array substrate that includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer includes at least one first wire. The first wire has an overlapping section and a connecting section connected to both ends of the overlapping section, and an extending direction of the overlapping section is different from an extending direction of the connecting section. The insulating layer covers the first metal layer, and the region of the insulating layer corresponding to the first wire is a convex ridge protruding in a direction away from the first metal layer. The second metal layer is provided on a side of the insulating layer facing away from the first metal layer and includes at least one second wire that intersects the convex ridge in the area of the convex ridge corresponding to the overlapping section.

Abstract: Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

Abstract: A semiconductor device has an N-type substrate, a through conductor penetrating the N-type substrate, a protection target circuit provided on the N-type substrate, and an ESD protection circuit provided on the N-type substrate. The protection target circuit and the ESD protection circuit are connected together to the through conductor.

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Abstract: A weather forecasting system has a data processing system that receives weather data from one or more sources and processes such data in conjunction with a weather forecasting algorithm in order to forecast weather for one or more geographic regions. In this regard, the weather data is input into a machine learning algorithm, which applies learned weights and relationships to the inputs in order to calculate at least one score indicating a probability that precipitation or other weather event will occur in the future within a certain time period (e.g., within the next 1 hour or some other unit of time) in one or more geographic regions. For each such geographic region, the weather forecasting logic may also predict the extent to which rain or other precipitation, lightning, or other weather event will occur during the time period.

Abstract: A method for calculating equivalent mechanical parameters of a film layer etching region is provided, by which more accurate equivalent mechanical parameters, which will be used in a process of manufacturing a display substrate of a terminal, may be obtained, thereby obtaining a display substrate with less defects. The method includes: selecting at least a part of the film layer etching region as an analysis region; establishing a planar model corresponding to the analysis region; performing grid division on the planar model at a first density; analyzing, by means of a finite element method, first simulation stresses of the planar model in simulated boundary conditions according to the actual mechanical parameters of a film layer material and the grid division of the first density; and calculating equivalent mechanical parameters.

Abstract: Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same wherein the capacitor may include a first conductive layer a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.