Abstract: An optoelectronic component with short circuit protection is provided, comprising a first electrode layer (1) with a plurality of segments (11, 12), which are arranged separately from one another, a functional layer (2) on the first electrode layer (1), which emits electromagnetic radiation when in operation, a second electrode layer (3) on the functional layer (2), a power supply (4) and a plurality of electrical connections (51, 52). In each case at least one of the plurality of electrical connections (51, 52) is arranged between the first power supply (4) and at least one of the plurality of segments (11, 12) of the first electrode layer (1) for electrical contacting of the first electrode layer (1). The power supply (4) has a first cross-section and each of the plurality of electrical connections (51, 52) has a second cross-section. The second cross-section is smaller than the first cross-section, and the electrical connections (51, 52) take the form of fuses.

Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract: The invention relates to an organic optoelectronic device, such as a display, lighting or signalling device, that is protected from the ambient air by a sealed encapsulation in the form of a thin film, and to a method for encapsulating such a device. An optoelectronic device (1) according to the invention is coated with a sealed multi-layer encapsulation structure (20) comprising alternating inorganic layers (21a to 26a) and organic layers (21b to 25b). According to the invention, the device is such that at least one of said organic layers consists of a crosslinked adhesive film (21b to 25b) based on a glue that can be crosslinked thermally or by electromagnetic radiation, the or each adhesive film having a thickness uniformly lower than 200 n, said thickness being obtained by passing the film, which is deposited and not yet cross-linked, through a vacuum, such that the total thickness of the encapsulation structure is minimized.

Abstract: An organic light emitting device having a light emitting unit that includes an anode layer, a second wire, an insulating layer, first and second organic light emitting layers and a cathode layer is provided. The anode layer includes first and second sub-electrodes and a first wire connecting the first and second sub-electrodes that are arranged in a first direction. The second wire is disposed between the first and second sub-electrodes. The insulating layer is disposed on the first and second sub-electrodes and the second wire, and has a plurality of openings to expose the first sub-electrode, the second sub-electrode and the second wire. The first and second organic light emitting layers are disposed in two openings. The cathode layer is disposed on the first and second organic light emitting layers, and the cathode layer fills another opening to electrically connect to the second wire through the another opening.

Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.

Abstract: In previously known imaging devices as in still and motion cameras, for example, image sensor signal response typically is linear as a function of intensity of incident light. Desirably, however, akin to the response of the human eye, response is sought to be nonlinear and, more particularly, essentially logarithmic. Preferred nonlinearity is realized in image sensor devices of the invention upon severely limiting the number of pixel states, combined with clustering of pixels into what may be termed as super-pixels.

Abstract: A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

Abstract: A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

Abstract: A non-volatile memory cell structure and a method of fabricating the same. The method comprising the steps of: fabricating a portion of a floating gate from one or more first metal local interconnection layer (LIL) slit contacts deposited on a patterned dielectric layer; and fabricating a portion of a control gate from one or more second metal LIL slit contacts deposited on the patterned dielectric layer; wherein the first and second metal LIL slit contacts form a capacitive structure between the floating gate and the control gate.

Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.

Abstract: An LED module includes a plurality of lighting sources each including a substrate, a first and second lead frames arranged on the substrate, an LED chip electrically connected to the first and the second lead frames, and an encapsulation covering the LED chip. The first lead frame of each of the lighting sources connects with the second lead frame of an adjacent lighting source electrically and mechanically.

Abstract: Disclosed is a sputtering target that can suppress the occurrence of anomalous discharge in the formation of an oxide semiconductor film by sputtering method and can continuously and stably form a film. Also disclosed is an oxide for a sputtering target that has a rare earth oxide C-type crystal structure and has a surface free from white spots (a poor appearance such as concaves and convexes formed on the surface of the sputtering target). Further disclosed is an oxide sintered compact that has a bixbyite structure and contains indium oxide, gallium oxide, and zinc oxide. The composition amounts (atomic %) of indium (In), gallium (Ga), and zinc (Zn) fall within a composition range satisfying the following formula: In/(In+Ga+Zn)<0.75.

Abstract: A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.

Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.

Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.

Abstract: Disclosed herein are a patterned substrate for a light emitting diode and a light emitting diode employing the patterned substrate. The substrate has top and bottom surfaces. Protrusion patterns are arranged on the top surface of the substrate. Furthermore, recessed regions surround the protrusion patterns. The recessed regions have irregular bottoms. Thus, the protrusion patterns and the recessed regions can prevent light emitted from a light emitting diode from being lost due to the total reflection to thereby improve light extraction efficiency.

Abstract: Methods and structures for a double-sided semiconductor structure using through-silicon vias (TSVs) are disclosed. The double-sided structure has functional circuits on both the front and back sides, interconnected by one or more TSVs. In some embodiments, multiple double-sided structures are combined to create 3D semiconductor structures with increased circuit density.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.