Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.

Abstract: Image sensor arrays may include bulk-charge-modulated-device (BCMD) sensor pixels. The BCMD sensor pixels may be used in back-side-illuminated (BSI) image sensors. A BCMD sensor pixel need not include a dedicated addressing transistor. The BCMD sensor pixel may include a gated drain reset (GDR) structure that is used to perform reset operations. The GDR structure may be shared among multiple pixels, which provides increased charge storage capacity for high resolution image sensors. A negative back body bias may be applied to the BCMD pixel array, allowing the depletion region under each BCMD pixel to extend all the way to the back silicon surface. Extending the depletion region by negatively biasing the back silicon surface may serve to minimize pixel crosstalk.

Abstract: Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.

Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.

Abstract: The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.

Abstract: Disclosed is an optical device including an optical member and a contact layer stacked on at least one of top and bottom surfaces of the optical member. The contact layer has at least one transparent conducting oxynitride (TCON) layer. The TCON consists of at least one of indium (In), tin (Sn), zinc (Zn), cadmium (Cd), gallium (Ga), aluminum (Al), magnesium (Mg), titanium (Ti), molybdenum (Mo), nickel (Ni), copper (Cu), silver (Ag), gold (Au), platinum (Pt), rhodium (Rh), iridium (Ir), ruthenium (Ru), and palladium (Pd).

Abstract: A light emitting device including a light emitting structure having a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a first electrode on the light emitting structure; and a photon escape layer on the light emitting structure. Further, the photon escape layer has a refractive index that is between a refractive index of the light emitting structure and a refractive index of an encapsulating material with respect to the light emitting structure such that an escape probability for photons emitted by the light emitting structure is increased.

Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.

Abstract: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and resolidified areas which likely have artifacts provided therein are overlapped by the subsequent beamlets. In this manner, the edge areas of the previously resolidified irradiated areas and artifacts therein are completely melted throughout their thickness. At least the subsequent beamlets are shaped such that the grains of the previously irradiated and resolidified areas which border the edge areas melted by the subsequent beamlets grow into these resolidifying edges areas so as to substantially reduce or eliminate the artifacts.

Abstract: A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction.

Abstract: The invention relates to a method for capping a MEMS wafer (1), in particular a sensor and/or actuator wafer, with at least one mechanical functional element (10). According to the invention, it is provided that the movable mechanical functional element (10) is fixed by means of a sacrificial layer (14), and that a cap layer (19) is applied to, in particular epitaxially grown onto, the sacrificial layer (14) and/or to at least one intermediate layer (17) applied to the sacrificial layer (14). The invention also relates to a capped MEMS wafer (1).

Abstract: A transistor array substrate includes a substrate, a pixel array, a plurality of resistors, and a plurality of semiconductor transistors. The pixel array, the resistors, and the semiconductor transistors are all disposed on the substrate. The pixel array includes a plurality of scan lines. Each resistor is electrically connected to one of the scan lines, and each semiconductor transistor is electrically connected to one of the scan lines and one of the resistors. The scan lines can receive a first voltage and a second voltage. The second voltage is higher than the first voltage.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate having conductors is then laminated over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. The light sheets may be formed to emit light from opposite surfaces of the light sheet, enabling it to be used in a hanging fixture to illuminate the ceiling as well as the floor. The light sheet provides a practical substitute for a standard 2×4 foot fluorescent ceiling fixture.

Abstract: The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

Abstract: A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall.

Abstract: This disclosure relates to devices and methods relating to coupled first and second device portions.

Abstract: An organic light-emitting display apparatus includes a substrate, a plurality of pixel electrodes formed on the substrate, a counter electrode formed to cover all of the plurality of pixel electrodes, organic light emitting layers disposed between the plurality of pixel electrodes and the counter electrode, an encapsulation substrate disposed above the substrate to cover the counter electrode, a sealant formed along edges of the substrate and the encapsulation substrate to seal a space formed between the substrate and the encapsulation substrate, a filler filled in the space formed between the substrate and the encapsulation substrate, and bus electrodes disposed on an inner surface of the encapsulation substrate facing the counter electrode. Each of the bus electrodes includes projecting portions and a base portion connecting the projecting portions to each other.

Abstract: Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (25,27) which drain finger is connected to a stack of one or more metal interconnect layers, (123,61,59,125) wherein a metal interconnect layer (123) of said stack is connected to a drain region (25) on the substrate, wherein said stack comprises a field plate (123, 125, 121) adapted to reduce the maximum magnitude of the electric field between the drain and the substrate and overlying the tip of said drain finger.