Abstract: Thin film transistors (TFTs) and methods of manufacturing the same. A TFT may include a floating channel on a surface of a channel and spaced apart from a source and a drain, and an insulating layer formed on the floating channel and designed to determine a distance between the floating channel and the source or the drain.

Abstract: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.

Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.

Abstract: A semiconductor device includes an undoped GaN layer (103) formed on a substrate (101), an undoped AlGaN layer (104) formed on the undoped GaN layer (103) and having a band gap energy larger than that of the undoped GaN layer (103), a p-type AlGaN layer (105) and a high-concentration p-type GaN layer (106) formed on the undoped AlGaN layer (104), and an n-type AlGaN layer (107) formed on the high-concentration p-type GaN layer (106). A gate electrode (112) which makes ohmic contact with the high-concentration p-type GaN layer (106) is formed on the high-concentration p-type GaN layer (106) in a region thereof exposed through an opening (107a) formed in the n-type AlGaN layer (107).

Abstract: Provided are a display device and a fabricating method thereof. The display device includes a substrate, a gate line, a common line, common electrodes, an insulating layer, a data line, a drain electrode, and pixel electrodes. The gate line is disposed in a first direction. The common line is disposed substantially parallel to the gate line. The common electrodes branch from the common line. The insulating layer covers the gate line, the common line, and the common electrodes. The channel patterns are disposed on the insulating layer to correspond to the gate electrode. The data line is disposed in a second direction. The drain electrode is electrically connected with the channel pattern. The pixel electrodes are formed of an opaque metal. Thus, the display device may improve contrast ratio.

Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Abstract: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED chip having the array of light emitting cells coupled in series is mounted on the LED package, it can be driven directly using an AC power source.

Abstract: A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

Abstract: A method of manufacturing a semiconductor device that includes forming a dummy gate insulating film and a dummy gate electrode on a semiconductor substrate having a channel-forming region. An etching treatment including a first treatment of treating the surface of the exposed surface of the insulating layer with an etching gas containing ammonia and hydrogen fluoride and a second treatment of decomposing and evaporating the product formed in the first treatment are included in removal step of the dummy gate insulating film.

Abstract: A white organic light emitting device having a stack structure of blue fluorescence and red/green phosphorescence is disclosed, in which efficiency of the blue fluorescence is improved to increase lifespan of the white organic light emitting device, color quality is improved, and power consumption is reduced.

Abstract: A semiconductor device is disclosed. In an embodiment, a semiconductor device includes a N-well within a P-well in a silicon layer, the silicon layer positioned atop a buried oxide layer of a silicon-on-insulator (SOI) substrate; a first source region and a second source region within a portion of the P-well; a first drain region and a second drain region within a portion of the P-well and within a portion of the N-well; and a gate positioned atop the N-well, wherein a lateral high field region is generated between the N-well and the P-well and a vertical high field region is generated between the gate and the N-well. A related method is disclosed.

Abstract: The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.

Abstract: A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance.

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.

Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.

Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.

Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.

Abstract: This invention provides a light-emitting diode (LED). The LED is electrically connected with a circuit board. The LED includes a light-emitting chip, an encapsulating element, a lead, and a heat insulating element. The encapsulating element encapsulates the light-emitting chip. The lead is coupled with the light-emitting chip and the circuit board. The lead and the encapsulating element form a first connecting place. The lead and the circuit board form a second connecting place. The heat insulating element is disposed between the first connecting place and the second connecting place.