Abstract: An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.

Abstract: A package structure of a long-distance sensor includes a substrate, a light-emitting chip, a sensing chip, two packaging gel bodies, a cap, and two sheltering devices. The substrate has a bearing surface. The light-emitting chip and the sensing chip are disposed on the bearing surface and separated from each other. The two packaging gel bodies cover the light-emitting chip and the sensing chip respectively. The top surface of each of the packaging gel bodies is formed with a lens portion and a shoulder portion. The cap is formed on the bearing surface and the packaging gel bodies and provided with a light-emitting hole and a light-receiving hole accommodating the lens portions and the shoulder portions of the top surfaces of the packaging gel bodies respectively. The two sheltering devices are disposed on the shoulder portions respectively for blocking light from passing through the shoulder portions.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.

Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light.

Abstract: An inverted-structure light-emitting element is provided. One embodiment of the invention disclosed in this specification is a light-emitting element including a cathode, a layer serving as a buffer over the cathode, an electron-injection layer over the layer serving as a buffer, a light-emitting layer over the electron-injection layer, and an anode over the light-emitting layer. The electron-injection layer includes an alkali metal or an alkaline earth metal. The layer serving as a buffer includes an electron-transport material. In the inverted-structure light-emitting element, contact of the alkali metal or alkaline earth metal included in a material of the electron-injection layer with the already formed cathode increases the driving voltage of an EL element and reduces emission efficiency. This problem becomes prominent particularly when the cathode includes an oxide conductive film. To prevent this, the layer serving as a buffer is provided between the cathode and the electron-injection layer.

Abstract: A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the device channel have been applied to advanced DRAM process nodes. The same etching process of the recess channel MOSFET device is applied to form the recess channel semiconductor NVM device. The tunneling oxides are grown on silicon surface after the recess channel hole etching process. The storing material is deposited into the recess channel holes with coupling dielectrics on top of the storing material. The gate material is then deposited and etched to form the control gate. Owing to the recess channel embedded below the silicon substrate, the scaling challenges such as gate channel length, floating gate interference, high aspect ratio for gate stack etching, and the mechanical stability of gate formation for the semiconductor NVM device can be significantly reduced.

Abstract: A magnetic memory of an embodiment includes: a first nonmagnetic layer including a first and second faces; a first and second wirings disposed on a side of the first face; a third wiring disposed on a side of the second face; a first transistor, one of the source and the drain being connected to the first wiring, the other one being connected to the first nonmagnetic layer; a second transistor, one of source and drain being connected to the second wiring, the other one being connected to the first nonmagnetic layer; a magnetoresistive element disposed between the first nonmagnetic layer and the third wiring, a first terminal of the magnetoresistive element being connected to the first nonmagnetic layer; and a third transistor, one of source and drain of the third transistor being connected to the second terminal, the other one being connected to the third wiring.

Abstract: A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit penetrating the interlayer insulating layers and the conductive patterns and crossing each other, an etch stop pad groove overlapping an intersection of the first slit and the second slit, arranged in the pipe gate, and connected to the first slit or the second slit, and slit insulating layers filling the first slit, the second slit and the etch stop pad groove.

Abstract: An integrated circuit has a substrate, a super-capacitor supported by the substrate, and a battery supported by the substrate. The super-capacitor includes a super-capacitor electrode and a shared electrode, and the battery has a battery electrode and the prior noted shared electrode. The super-capacitor and battery form at least a part of a monolithic integrated circuit.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.

Abstract: According to one embodiment, a magnetic memory device includes a first insulating film provided on a semiconductor region, and having a portion located in a memory cell array area and thicker than a portion located in a peripheral circuit area, a plurality of conductive plugs located in the memory cell array area and provided in the first insulating film, stacked structures located in the memory cell array area, provided on the conductive plugs, and each having layers including a magnetic layer, and transistors located in the peripheral circuit area, and each including a gate electrode provided on the semiconductor region and covered with the first insulating film, wherein a thickness t0 from a main surface of the semiconductor region to a lower surface of each stacked structure is greater than a predetermined value.

Abstract: A light emitting device includes a semiconductor light emitting element; a mounting substrate; a support substrate; a joining layer which joins the semiconductor light emitting element and the mounting substrate together, is a sintered body of metal particles, and has a pore; and a joining layer which joins the mounting substrate and the support substrate together, is a sintered body of metal particles, and has a pore, in which a porosity of the joining layer is lower than a porosity of the joining layer.

Abstract: A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping, after removal of the dummy gate and before a replacement metal gate is formed.

Abstract: Provided is a light receiving/emitting element and a light receiving/emitting apparatus that can be easily manufactured and allow high-sensitivity detection. The light receiving/emitting element is configured to include a first organic photoelectric conversion unit and a second organic photoelectric conversion unit that is disposed on the first organic photoelectric conversion unit and is different in spectral sensitivity from the first organic photoelectric conversion unit, wherein one of the first organic photoelectric conversion unit and the second organic photoelectric conversion unit acts as a light receiving unit and the other acts as a light emitting unit. The light receiving/emitting apparatus is configured to have the light receiving/emitting element mounted thereon.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.

Abstract: The present application relates to spirobifluorene derivatives of a formula (I), to the use thereof in electronic devices, and to processes for preparing said derivatives.

Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Abstract: A semiconductor device according to an embodiment includes: a first GaN based semiconductor layer; a second GaN based semiconductor layer disposed on the first GaN based semiconductor layer and having a bandgap larger than that of the first GaN based semiconductor layer; a source electrode disposed on the second GaN based semiconductor layer; a drain electrode disposed on the second GaN based semiconductor layer; a p-type third GaN based semiconductor layer disposed between the source electrode and the drain electrode on the second GaN based semiconductor layer; a gate electrode disposed on the third GaN based semiconductor layer; and a p-type fourth GaN based semiconductor layer disposed between the gate electrode and the drain electrode on the second GaN based semiconductor layer and disposed separated from the third GaN based semiconductor layer.

Abstract: A circuit protection structure applied to a gate driver that is in a display panel (GIP) is provided. The gate driver has a first metal layer, a first isolation layer, a semiconductor layer, a second metal layer, and a second isolation layer. The first metal layer, the first isolation layer, the semiconductor layer, the second metal layer, and the second isolation layer are stacked in sequence. The circuit protection structure includes a protection layer. The protection layer is located on the second isolation layer.

Abstract: Disclosed is a light-emitting device comprising a light-emitting stack having a length, a width, a first conductivity type semiconductor layer, an active layer on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer on the active layer, wherein the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are stacked in a stacking direction. A first electrode is coupled to the first conductivity type semiconductor layer and extended in a direction parallel to the stacking direction and a second electrode is coupled to the second conductivity type semiconductor layer and extended in a direction parallel to the stacking direction. A dielectric layer is disposed between the first electrode and the second electrode.