Patents Examined by Su C. Kim
  • Patent number: 10164141
    Abstract: A semiconductor device includes a carrier wafer, a device layer, a first semiconductor layer and a second semiconductor layer. The device layer is disposed on the carrier wafer. The first semiconductor layer is disposed on the device layer, and has a first side face and a second side face opposite to the first side face, in which the first side face is adjacent to the device layer. The second semiconductor layer is disposed on the first semiconductor layer, and has a third side face and a fourth side face opposite to the third side face, in which the fourth side face of the second semiconductor layer is adjacent to the second side face of the first semiconductor layer, and the second semiconductor layer is implanted and annealed.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Nan Tu, Yu-Lung Yeh, Hsing-Chih Lin, Chien-Chang Huang
  • Patent number: 10154626
    Abstract: A light-emitting diode (LED) for plant illumination includes a substrate, and a PN-junction light-emitting portion over the substrate. The light-emitting portion has a strained light-emitting layer with a component formula of GaXIn(1-X)AsYP(1-Y) (0<X<1 and 0<Y<1), and a barrier layer, forming a 2˜40-pair alternating-layer structure with the strained light-emitting layer.
    Type: Grant
    Filed: May 14, 2017
    Date of Patent: December 18, 2018
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hongliang Lin, Chaoyu Wu, Yi-Jui Huang, Chun-I Wu, Ching-Shan Tao, Junkai Huang, Duxiang Wang
  • Patent number: 10147736
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a semiconductor film extending in stacking direction of the stacked body; an interconnect layer extending in the stacking direction of the stacked body and a first direction crossing the stacking direction; and an insulating film. The interconnect layer includes: a core film extending in the stacking direction and the first direction; an intermediate film provided integrally between the core film and the plurality of electrode layers and between the core film and the substrate; and a first conductive film provided integrally between the intermediate film and the plurality of electrode layers and between the intermediate film and the substrate, being in contact with the substrate, and having an upper surface flush with an upper surface of the intermediate film.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshihiko Iinuma
  • Patent number: 10147778
    Abstract: A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 4, 2018
    Assignee: Japan Display Inc.
    Inventor: Toshihiro Sato
  • Patent number: 10141394
    Abstract: The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 27, 2018
    Assignee: IMEC vzw
    Inventor: Mikael Detalle
  • Patent number: 10141427
    Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Gyeom Kim, Hong-Sik Yoon, Bon-Young Koo, Wook-Je Kim
  • Patent number: 10141363
    Abstract: When a trench that penetrates a semiconductor substrate in a scribe region in a solid-state imaging element of a back side illumination type, occurrence of contamination of the solid-state imaging element caused by an etching step for foaming the trench or a dicing step for singulating a semiconductor chip is prevented. When a silicide layer that covers a surface and the like of an electrode of a transistor is formed, in order to prevent formation of the silicide layer that covers a main surface of the semiconductor substrate in the scribe region, the main surface of the semiconductor substrate is covered with an insulation film before a forming step for the silicide layer.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Sekikawa
  • Patent number: 10134830
    Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Hideaki Kawahara, Sameer P. Pendharkar
  • Patent number: 10134635
    Abstract: Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped through-silicon-via (TSV), said stress relieving stepped TSV being formed by: forming first mask layers on a top surface and a bottom surface of a silicon layer, forming a via hole through the silicon layer at exposed regions defined by the first mask layers, and removing the first mask layers. The formed via hole may be filled with metal, second mask layers may be formed covering top and bottom surfaces of the silicon layer and a portion of top and bottom surfaces of the metal filling the formed via hole, and metal may be removed from the top and bottom surfaces of the metal exposed by the second mask layers to a depth of less than half a thickness of the silicon layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: November 20, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Bora Baloglu, Ronald Patrick Huemoeller
  • Patent number: 10134811
    Abstract: Image sensors include a color photo-sensing photoelectric conversion device, a first color filter and a second color filter disposed under the color photo-sensing photoelectric conversion device, a first photodiode and a second photodiode disposed under the first color filter and the second color filter, respectively, a first light guide member disposed between the first color filter and the first photodiode, and a second light guide member disposed between the second color filter and the second photodiode.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu Sik Kim, Satoh Ryuichi, Gae Hwang Lee
  • Patent number: 10134861
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
  • Patent number: 10128235
    Abstract: A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10128314
    Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Francesco La Rosa, Julien Delalleau
  • Patent number: 10121736
    Abstract: A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 6, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Kuo-Ting Lin, Chia-Wei Chang
  • Patent number: 10121669
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 6, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jinhua Liu
  • Patent number: 10115682
    Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 30, 2018
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chun-Hsiao Li, Wei-Ren Chen, Hsueh-Wei Chen
  • Patent number: 10115594
    Abstract: A method of forming fine island patterns of semiconductor devices includes: forming a plurality of first mask pillars on a hard mask layer on a substrate; forming an upper buffer mask layer on the hard mask layer to cover the first mask pillars; patterning a plurality of islands in the upper buffer mask layer; separating each of the islands into a plurality of sub-islands; etching the upper buffer mask layer to form a plurality of second mask pillars on the hard mask layer; etching an exposed portion of the hard mask layer exposed by the first mask pillars and the second mask pillars until portions of the substrate are etched; and removing the first mask pillars, the second mask pillars, and remaining portions of the hard mask layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 30, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Chiang-Lin Shih, Chih-Ching Lin
  • Patent number: 10103249
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins. The source/drain structure has a top portion with a W-shape cross section for forming a contact landing region. The semiconductor device may further include a plurality of capping layers located on a plurality of recessed portions of the top portion.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
  • Patent number: 10096471
    Abstract: A method for fabricating a structure having surfaces exposed to plasma in a substrate processing system includes providing a sacrificial substrate having a first shape, machining the substrate into a second shape, the second shape having dimensions corresponding to a desired final shape of the structure, depositing a layer of material on the substrate, machining first selected portions of the layer of material to expose the substrate within the layer of material, removing remaining portions of the substrate, and machining second selected portions of the layer of material into the structure having the desired final shape without machining the surfaces of the structure that are exposed to plasma during processing.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 9, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Justin Charles Canniff
  • Patent number: 10096635
    Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: October 9, 2018
    Assignee: XINTEC INC.
    Inventors: Wei-Ming Chien, Po-Han Lee, Tsang-Yu Liu, Yen-Shih Ho