Abstract: Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the arbitrary expression satisfies one or more analyzability conditions is performed. Based on verifying the arbitrary expression satisfies the one or more analyzability conditions, the irrelevant domain for the coverage item is calculated based on the arbitrary expression. An enhanced functional coverage model that excludes the irrelevant domain for the coverage item is generated and used to perform the functional coverage analysis on the IC design.

Abstract: The present disclosure relates to a method for probabilistic simulation of a microelectronic device, said method being implemented automatically by an electronic processing device and including the following steps: a) defining a plurality of first samples of the device from a probability distribution of at least one physical parameter of the device; b) for each first sample, determining, through an electrical simulation method, the value of at least one operating variable of the device; c) defining, by regression from values of the physical parameters and operating variables of the first samples simulated in step b), a mathematical model approximating the response of the electrical simulation method.

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Abstract: A system may include an image clustering engine and a cluster provision engine. The image clustering image may be configured to access a set of circuit images and cluster the circuit images into different groups via an unsupervised learning process, wherein clustering by the unsupervised learning process is invariant to each invariant property of an invariant property set. A given invariant property in the invariant property set may correspond to a given image transformation, the invariant properties in the invariant property set may be discrete, and the total number of invariant properties in the invariant property set may be finite. The cluster provision engine may be configured to provide the clustered circuit images for further processing or analysis by an electronic design automation (EDA) application.

Abstract: In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.

Abstract: Provided is a method for fabricating a semiconductor device including performing an OPC process to an IC layout pattern to generate a post-OPC layout pattern. In some embodiments, the method further includes applying an MPC model to the post-OPC layout pattern to generate a simulated mask pattern. By way of example, the simulated mask pattern is compared to a mask pattern calculated from a target wafer pattern. Thereafter, and based on the comparing, an outcome of an MPC process is determined.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: The disclosed technology includes, among other innovations, a framework for resource efficient compilation of higher-level programs into lower-level reversible circuits. In particular embodiments, the disclosed technology reduces the memory footprint of a reversible network implemented in a quantum computer and generated from a higher-level program. Such a reduced-memory footprint is desirable in that it addresses the limited availability of qubits available in many target quantum computer architectures.

Abstract: Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

Abstract: A system may include a quantum model engine configured to generate (e.g., load or instantiate) a quantum computing model to represent an electronic design automation (EDA) process for a circuit design. The EDA process may be a multi-patterning process to assign colors to geometric elements of the circuit design. The quantum computing model may include quantum particle types that may be defined to prohibit non-physical states in the quantum computing model from occurring. The quantum model engine may also be configured to generate a color assignment for the geometric elements of the circuit design through the quantum computing model. The system may also include a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.

Abstract: In a consumer arrangement (2) with a power supply (4) with power supply input (6), with a consumer (10) which is supplied with an output power (A) by the power supply (4), wherein the power supply (4) contains a PFC module (12) with a DC link (14), wherein the PFC module (12) contains a regulator (16) for supplying the DC link (14), a characteristic parameter (K) correlated with the output power (A) required by the consumer (10) is fed back into the regulator (16). In a method for operating a consumer arrangement (2) with a power supply (4), with a consumer (10) which is supplied with an output power (A) by the power supply (4), wherein the power supply (4) contains a PFC module (12), wherein the PFC module (12) contains a regulator (16), a characteristic parameter correlated with the output power (A) required by the consumer (10) is fed back into the regulator (16).

Abstract: A charging state display controller recognizing and displaying that a high voltage battery of an electric vehicle is being used, may include a receiving unit receiving operation signals output from controllers using the high voltage battery when the high voltage battery is in a using mode, a signal determination unit determining whether or not the number of the operation signals received by the receiving unit satisfies a predetermined condition, and a control unit controlling on/off of a charging state indicator in accordance with whether or not the number of operation signals satisfies the predetermined condition.

Abstract: A method of selecting relative timing constraints for enforcing in an asynchronous circuit is presented. The method includes selecting one or more sets of relative timing constraints, which include a first set of relative timing constraints, wherein the first set of relative timing constraints meets the following criteria: i) the first set is suitable for preventing the asynchronous circuit from entering two or more bad states in which a correctness property of the asynchronous circuit is violated, and ii) the first set comprises a plurality of relative timing constraints, wherein each relative timing constraint within the first set is associated with a bad state whose associated relative timing constraints comprise this relative timing constraint but no other relative timing constraint that is implied by another relative timing constraint in the first set.

Abstract: A method for predicting post-placement timing-analysis results includes obtaining, for a logic design, logic-synthesis data and logic-planning data. The method also includes inputting, into a neural network, the logic-synthesis data and logic-planning data. The neural network is trained to correlate logic-synthesis data and logic-planning data with post-placement timing-analysis results. The method also includes receiving, from the neural network, predicted post-placement timing-analysis results.

Abstract: Techniques for generating a layout of a multi-port memory cell are provided. A specification describing at least on port within a memory cell is defined. A base memory cell including at least one extension point is modeled. A port that interfaces with the base memory cell is identified from the specification. An electrical interface between the identified port and an extension point of the base memory cell is modeled. In some embodiments, a design bucket is selected from among a predefined set of design buckets based on a count of ports within the memory cell, as described by the specification. Each design bucket corresponding to a respective layout template including the base memory cell and a respective maximum count of ports. Each electrical interface including a port described in the specification of the memory cell is modeled based on the selected design bucket and the respective layout template.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: A method for reducing voltage hot spots in a power grid for a circuit design is implemented on a computer system and includes the following steps. The computer system (e.g., an EDA tool) accesses the circuit design. The circuit design includes a power grid that distributes power throughout the circuit design. The computer system identifies spots in the power grid with excessive voltage drops. These will be referred to as hot spots. The power grid is augmented by adding local conductors at the hot spots. These local conductors provide additional electrical paths through the power grid at the hot spots. This in turn reduces the voltage drops at the hot spots.

Abstract: Systems and techniques are described for transparent hierarchical routing in an integrated circuit (IC) design. A logical netlist can be analyzed in the IC design to identify endpoints of a physical route that crosses at least one physical hierarchy boundary. Next, a set of routing shapes can be created to electrically connect the endpoints of the physical route. The set of routing shapes can then be transformed to corresponding routing shapes in each physical hierarchy context along the physical route.

Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and second boundaries are further positioned in accordance with an integer multiple of the first pitch when the computer is invoked to form the plurality of cells representing the circuit.

Abstract: A method for modeling glitch of a logic gate is provided. An input glitch with a glitch width is obtained from the logic gate. The glitch width is scaled by a first scaling factor when the glitch width is greater than or equal to a first threshold width. The glitch width is scaled by a second scaling factor when the glitch width is less than the first threshold width and greater than or equal to a second threshold width. An output glitch with the scaled glitch width is provided for the logic gate. The scaled glitch width is greater than 0. The first threshold width is greater than the second threshold width, and the second scaling factor is smaller than the first scaling factor.