Abstract: In one embodiment, a computing system may access design data of a printed circuit board to be produced by a first manufacturing process. The system may analyze the design data of the printed circuit board using a machine-learning model, wherein the machine-learning model is trained based on X-ray inspection data associated with the first manufacturing process. The system may automatically determine one or more corrections for the design data of the printed circuit board based on the analysis result by the machine-learning model.

Abstract: In accordance with an embodiment, a wireless power transmitter includes a charging surface, a transmitting antenna configured to generate an electromagnetic field extending above the charging surface, a sensing array disposed between the transmitting antenna and the charging surface, and a controller coupled to the sensing array. The sensing array includes a plurality of sensors. Each sensor of the plurality of sensors is configured to generate a respective signal indicative of a strength of the electromagnetic field. The controller is configured to detect a presence of a metallic object, other than a receiving antenna of a power receiver, in the electromagnetic field based on the respective signal generated by one or more sensors of the plurality of sensors.

Abstract: A battery pack management system includes a controller, an isolation unit, a plurality of battery pack management units, and a plurality of battery packs. The plurality of battery pack management units are connected in series by a first daisy chain, and the plurality of battery pack management units are also connected in series by a second daisy chain. The first daisy chain transmits sampled data that is collected by the battery pack management units from corresponding battery packs and transmits control instructions of the controller. The second daisy chain transmits a failure prompt signal which is generated by a battery pack management unit that detects a failure. A first battery pack management unit and a last battery pack management unit of the plurality of battery pack management units connected in series are connected to the controller through the isolation unit.

Abstract: There is provided a system and method of examination of a semiconductor specimen using an examination recipe. The method includes obtaining a registered image pair, for each design-based structural element associated with a given layer, calculating an edge attribute, using a trained classifier to determine a class of the design-based structural element, and generating a layer score usable to determine validity of the registered image pair. There is also provided a system and method of generating the examination recipe usable for examination of a semiconductor specimen.

Abstract: Several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift, tilt of a Bossung curve of a portion of a design layout used in a patterning process for imaging that portion onto a substrate using a lithographic apparatus. The methods include determining or adjusting one or more characteristics of one or more assist features using the one or more rules based on one or more parameters selected from a group consisting of: one or more characteristics of one or more design features in the portion, one or more characteristics of the patterning process, one or more characteristics of the lithographic apparatus, and/or a combination selected from the foregoing.

Abstract: System and methods for an edge-based camera are disclosed. Semiconductor layout designs are a representation of an integrated circuit that are used to manufacture the integrated circuit. Parts of the layout design, such as points of Interest (POIs), may be subject to analysis with regard to a downstream application, such as hotspot detection. Unlike pixel-based characterizations, POIs are characterized using topological features indicative of quantized values and dimensional features indicative of analog values. For example, an edge may be characterized using a set of relations, which characterizes corners and polygons (including the polygon on which the POI resides and external polygons). In turn, the set of relations may be used to define image representations, including images in different directions relative to the POI (including cardinal and ordinal image). In this way, the topological/dimensional characterization of the POI may be used to analyze the POI in the layout design.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for autonomous verification of circuit design for IoT-type devices, which may include, for example, IoT-type devices operating in resource constrained or like environments.

Abstract: A cable management system for an overhead EVSE employs a lever-latch on the EV connector. A controller and motor mechanism is employed to lower the connector to an ADA compliant position or a pre-established height which is typically four feet. For an overhead system which employs a shuttle which slides along a track, the connector may then be grasped to pull the shuttle to a selected position along the track. The latch is depressible to extend the service cable to the connector so that the connector may be positioned and connected at the EV inlet. When the connector is unlatched from the EV inlet, the latch may be depressed to retract the connector to the pre-established height or ADA position. The latch requires a force of less than 5 lbs. for activation.

Abstract: This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.

Abstract: The present invention can determine in advance whether the design RULE is violated by checking the design conditions and design requirements required by the client and the project in the plant engineering stage on the 3D CAD model. The present invention can improve the design quality of plant engineering and minimizing the modification of the drawings occurring during construction by checking whether the various data of the vendor drawings received by the EPC company are accurately reflected to the 3D CAD modeling design.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: A vehicle power supply device includes a relay controller. When a low voltage switching request is made to set a mode for supplying electric power from a switching module group to a low voltage power supply, the relay controller is configured to perform in sequence a first process of switching a first main relay and a second main relay to an open state, a second process of connecting a first switching relay to a second electrode terminal of the low voltage power supply and switching a second switching relay to a closed state, a third process of switching a precharge relay to a closed state and switching a third switching relay to a closed state, a fourth process of switching the second main relay to a closed state, and a fifth process of switching the precharge relay to an open state.

Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.

Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the merged set of constraints. The STA also includes determining a soft breaking point for the loop in the MMMC view for timing propagation and settling. The STA maintains consistency of breaking points across SMSC and MMMC views.

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.

Abstract: A method of generating an IC layout diagram includes positioning one or more cells in an IC layout diagram and overlapping the one or more cells with a first metal layer cut region based on a first metal layer cut region alignment pattern. The first metal layer cut region alignment pattern includes a pattern pitch equal to a height of the one or more cells.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.