Abstract: Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well.

Abstract: An automatic parking system with charging function includes an in-out space, parking levels, loading boards, and a conveyer. Each parking level includes parking spaces, each parking space has a charging pile and a power supply interface electrically connected with the charging pile. Each loading board includes a board portion, a power receiving interface, a charging cable for charging the electric vehicle, and a support foot. The conveyer includes a lifting platform and an automated guided vehicle, the automated guided vehicle is configured to drive into a position under the board portion and support the loading board upward so as to carry the loading board, when the loading board is carried to a predetermined position of the corresponding parking space, the automated guided vehicle is lowered to make the support foot be supported on the corresponding parking space and the power receiving interface mate with the corresponding power supply interface.

Abstract: The electric vehicle holder includes a housing; clamping arms are respectively inserted into two sides of the housing; the electric vehicle holder further includes an electric mechanism, a circuit board, and a power supply module; a normally open circuit configured to control the electric mechanism to drive the two clamping arms away from each other is arranged on the circuit board; and a detector is further arranged in the housing. By arranging the electric mechanism and arranging the normally open circuit on the circuit board, when the electric vehicle holder is powered on, the two clamping arms are opened; since the clamping arms do not need to be opened manually, the installation of a tablet electronic device is convenient.

Abstract: A system and method for creating chip layout are described. In various embodiments, a standard cell uses unidirectional tracks for power connections and signal routing. At least two tracks of the metal one layer using a minimum width of the metal one layer are placed within a pitch of a single metal gate to provide a standard cell with a two to one “gear ratio” or greater. A power signal and a ground reference signal in the metal one layer are routed in a same metal one track to provide area for other signal routing. Multiple standard cells are placed in a multi-cell layout with routes in one or more of the metal two layer and the metal three layer using minimum lengths for power connections. The layout includes no power grid with a fixed pitch.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: Distributed energy storage within the distribution network of an electric power network at least partially supplied by time varying and unpredictable generation sources provides smoothing of energy flow within the distribution network. The distributed energy storage may include a plurality of distributed energy storage units operating under the control of a single controller or regional controllers. The distributed energy storage units may operate as groups of units or as separate units.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting a first shadow element representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

Abstract: An electronic apparatus and a layout method for an integrated circuit (IC) are provided. The layout method for the IC includes: receiving layout information, analyzing the layout information to obtain a plurality of blank areas in the IC; presetting a plurality of dummy blocks which respectively have a plurality of sizes; selecting at least one of the dummy blocks to fill in each of the blank areas based on a center position of each of the blank areas according to a size of each of the blank areas and generating updated layout information; performing a layout density checking operation on the updated layout information to generate a checking result; and shrinking sizes of a plurality of setting dummy blocks in the IC according to the checking result and generating output layout information.

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a two stage routing analysis, wherein a first stage analysis is an intra-row routing analysis and a second stage is an inter-row routing analysis. Embodiments may also include generating an optimized routing of the one or more nets and displaying the optimized routing at a graphical user interface.

Abstract: The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.

Abstract: A system for a vehicle including a traction battery, electrical loads, and a controller configured to, during a charge operation, activate the loads such that charge current output by a charger is consumed by the loads and charge current input to the battery approaches zero to update a state of charge (SOC) value of the battery, and deactivate the loads upon completion of the update such that charge current input to the battery increases.

Abstract: According to one embodiment, a circuit design supporting method comprising: generating first determination information based on first information obtained by a cycle based logic simulation; extracting glitch generation sources; generating second determination information based on second information obtained based on the first information by considering glitch; comparing the first and the second determination information to each other and determining whether or not a comparison result satisfies a condition; and performing the generating the second determination information and the determining for each of the glitch generation sources and presenting, to a user, one or a plurality of glitch generation sources in which the comparison result satisfies the condition.

Abstract: Methods, systems and computer program products for generating a functional logic cone signature for circuit analysis are provided. Aspects include for each of a plurality of portions of a circuit diagram of a circuit, tracing the respective portion of the circuit diagram to identify circuit components associated with the respective portion of the circuit diagram from a starting latch to one of one or more source latches. Circuit components include circuit elements and circuit connections. Aspects include generating an ASCII representation of the respective identified circuit components for each of the plurality of portions of the circuit diagram of the circuit. Aspects include generating a plurality of hash values by applying a hashing function to each ASCII representation. Each hash value corresponds to one of the plurality of portions of the circuit diagram. Aspects also include storing the hash values in a data structure.

Abstract: A testing apparatus includes a chip carrying device and a pressing device. The chip carrying device includes a circuit board and a plurality of electrically connecting units that are disposed on the circuit board and each can receive a chip. The pressing device includes a cover, an abutting member, and an airtight member. The cover is disposed on the circuit board to jointly define an accommodating space accommodating the abutting member and the electrically connecting units. The airtight member is arranged between the cover and the circuit board to seal the accommodating space. The cover has at least one exhaust hole. When an air suction apparatus exhausts air in the accommodating space through the at least one exhaust hole, the cover is abutted against the airtight member, and the abutting member is abutted against the chips to connect each of the electrically connecting units and the corresponding chip.

Abstract: In accordance with an embodiment, a wireless power transmitter includes a charging surface, a transmitting antenna configured to generate an electromagnetic field extending above the charging surface, a sensing array disposed between the transmitting antenna and the charging surface, and a controller coupled to the sensing array. The sensing array includes a plurality of sensors. Each sensor of the plurality of sensors is configured to generate a respective signal indicative of a strength of the electromagnetic field. The controller is configured to detect a presence of a metallic object, other than a receiving antenna of a power receiver, in the electromagnetic field based on the respective signal generated by one or more sensors of the plurality of sensors.

Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.