Patents Examined by Suresh Memula
  • Integrated circuits including standard cells and methods of manufacturing the integrated circuits
    Patent number: 10990740
    Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 27, 2021
    Inventors: Jin-Tae Kim, Sung-We Cho, Tae-Joong Song, Seung-Young Lee, Jin-Young Lim
  • Method and apparatus for integrated circuit mask patterning
    Patent number: 10990744
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Digital Rights Management for printed circuit boards
    Patent number: 10984165
    Abstract: Embodiments may provide Digital Rights Management techniques, not to make the reverse engineering process harder, but rather to provide detection of reverse engineering of PCBs, such as by copying of layers of trace layout, so as to enable pursuing legal remedies against the violators. For example, in an embodiment, a method of information encoding may be implemented in a computer comprising a processor, memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor, the method may comprise receiving, at the computer system, information to be encoded in a printed circuit board wiring trace layout and laying out, at the computer system, a plurality of printed circuit board wiring traces so as to encode the received information.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventor: Oded Margalit
  • System for designing semiconductor circuit and operating method of the same
    Patent number: 10970452
    Abstract: Provided are a system for designing a semiconductor circuit and an operating method of the same. The system includes a working memory loading a clustering application for generating a cluster, based on instances respectively corresponding to cells of the semiconductor circuit, and loading a design tool for placing the cells. The clustering application, when an output terminal of a first instance is connected to a second instance and the number of instances connected to the output terminal of the first instance is one, classifies the first instance and the second instance into a candidate group pair. The clustering application, when all instances connected to an input terminal of the second instance are classified into the candidate group pair with the second instance, generates the cluster including the first instance and the second instance.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyounghwan Lim, Hyungock Kim, Heeyeon Kim, Dongkwan Han
  • Apportionment aware hierarchical timing optimization
    Patent number: 10970455
    Abstract: Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Adil Bhanji, Nathaniel Douglas Hieter
  • Circuit design method and associated computer program product
    Patent number: 10943047
    Abstract: A circuit design method is provided, including the steps of: designing a plurality of paths, wherein each path includes a plurality of elements; determining a specific path of the plurality of paths by performing a timing analysis; replacing the specific element in the specific path with the configurable logic gate array cell; and selectively changing a connection mode of a metal layer to make the configurable logic gate array cell have another function. The timing analysis includes: for each path of the plurality of paths, determining whether a chip area meets a constraint condition and whether a timing violation will occur when a specific element in each path is replaced with a configurable logic gate array cell; and when both conditions are met, determining that path as the specific path.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Shih-Hsiang Tai
  • Planning method for power metal lines
    Patent number: 10936784
    Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 2, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Devices, systems, and methods for integrated circuit verification
    Patent number: 10937203
    Abstract: A method includes storing first macros that define colors of text generated during a simulation of a design under test (DUT) of an integrated circuit (IC). The method includes mapping second macros to the first macros based on a plurality of colors, where each of the plurality of colors is associated with one of a plurality of report messages generated by executing the second macros. The method includes conducting the simulation of the DUT, and displaying, based on the conducted simulation, the plurality of report messages in a format where each of the plurality of report messages is displayed in a color associated with the report message.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 2, 2021
    Assignee: E-INFOCHIPS LIMITED
    Inventors: Babun Chandra Pal, Rajesh Kumar Panda
  • Methodology using Fin-FET transistors
    Patent number: 10922467
    Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 16, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Bohai Liu, Gang Ni, Chunlei Zhu, Gary K. Yeap
  • Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts
    Patent number: 10922469
    Abstract: Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yuan-Kai Pei, Gautam Kumar, Gerard Tarroux
  • Wireless power receivers that receive power during traversal of a prescribed path
    Patent number: 10916974
    Abstract: According to various embodiments, a moving wireless power receiver is configured to receive power wirelessly based on a prescribed path of the wireless power receiver. A prescribed path that a moving wireless power receiver traverses is identified. Further, at least one element of the wireless power receiver is controlled based on the prescribed path to change an amount of power received at the wireless power receiver from incident power transmitted by one or more wireless power transmitters. Specifically, the at least one element can be controlled to change the amount of power received at the wireless power receiver as either or both a posture and a position of the wireless power receiver change with respect to the one or more wireless power transmitters as the wireless power receiver traverses the prescribed path.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 9, 2021
    Assignee: The Invention Science Fund I LLC
    Inventors: Daniel Arnitz, Lawrence F. Arnstein, Joseph Hagerty, Guy S. Lipworth
  • Method and apparatus for relocating design modules while preserving timing closure
    Patent number: 10909296
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 2, 2021
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Method and system for digital direct imaging, image generating method and electronic device
    Patent number: 10909431
    Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 2, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chien-Hung Lin, Yu-Sheng Lee, Yung-Chao Chen, Chih-Wei Hsu
  • Electrical charging system for a robot
    Patent number: 10906419
    Abstract: A docking station for charging a robot including an electrical charger assembly affixed to the charger docking station and configured to mate with an electrical charging port on the robot when the robot is docked at the docking station for charging. There is at least one compliant member interconnecting the electrical charger assembly to a portion of the docking station to allow movement of the electrical charger assembly relative to the electrical charging port on the robot when the robot is mating with the docking station.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 2, 2021
    Inventors: Hian Kai Kwa, Christina Nicole Fong, Michael Sussman
  • Wire orientation-based latch shuddling
    Patent number: 10902178
    Abstract: Methods, systems and computer program products for providing wire orientation-based latch shuddling are provided. Aspects include determining a classification of each latch of a plurality of latches as having a vertical orientation, a horizontal orientation or a mixed orientation. Aspects also include clustering the plurality of latches into one or more clusters based on the classifications of the plurality of latches. Each of the one or more clusters includes a unique set of latches of the plurality of latches. Aspects also include shuddling each of the one or more clusters around a local clock buffer within a layout. Each cluster of the one or more clusters is shuddled in a configuration around the local clock buffer based on the classifications of the corresponding unique set of latches of the plurality of latches.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Surprise, Gerald Strevig, III, Shawn Kollesar
  • Computer-implemented method and computing system for designing integrated circuit by considering timing delay
    Patent number: 10902168
    Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The method includes generating wire data corresponding to a net included in an integrated circuit, the wire data including metal layer information of a wire corresponding to the net and physical information of the wire, performing timing analysis using the physical information of the wire included in the wire data to generate timing analysis data, and changing a layout of the integrated circuit according to the timing analysis data.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-pil Lee, Bong-il Park, Moon-su Kim, Sun-ik Heo
  • Method and system for automatically generating interactive wiring diagram in an industrial automation environment
    Patent number: 10895871
    Abstract: A method and system for automatically generating interactive wiring diagram in an industrial automation environment are disclosed. The method includes acquiring real-time data associated with devices commissioned in a plant from one or more sensing units disposed at the respective devices. The method also includes determining connections between the devices in the plant based on the acquired real-time data using a lookup table. The method includes generating a wiring diagram of the plant based on the determined connections between the devices. The wiring diagram represents the devices located in the plant and physical connections between the devices. The method includes dynamically generating interactive wiring diagrams by superimposing the wiring diagram with the device connectivity status information associated with respective connections between the devices.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 19, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Mahantesh Ganachari
  • Offline analysis of hierarchical electronic design automation derived data
    Patent number: 10891412
    Abstract: An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sheshashayee K. Raghunathan, Thomas S. Guzowski, Nathan Buck, Kerim Kalafala, Jack DiLullo, Debra Dean
  • Object identification and comparison
    Patent number: 10890540
    Abstract: A method including selecting a shaped feature from a set of shaped features, each shaped feature of the set of shaped features having a set of points on a perimeter of the shape of the shaped feature, creating a plurality of shape context descriptors for the selected shaped feature, wherein each shape context descriptor provides an indication of a location in a shape context descriptor framework of a first focus point of the set of points in relation to a second point of the set of points, and identifying a shaped feature from the set of shaped features having a same or similar shape as the selected shaped feature based on data from the plurality of shape context descriptors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 12, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Adrianus Cornelis Matheus Koopman, Scott Anderson Middlebrooks, Willem Marie Julia Marcel Coene
  • Systems and methods for determining fabrication loss of segmented designs using paintbrush patterns
    Patent number: 10885262
    Abstract: In some embodiments, a design verification system is provided that is configured to perform actions for ensuring fabricability of a segmented design. The design verification system searches a proposed segmented design for a paintbrush pattern to determine a positive paintbrush loss, and searches for an inverse paintbrush pattern to determine a negative paintbrush loss. The design verification system combines the positive paintbrush loss and the negative paintbrush loss to obtain a total paintbrush loss that indicates whether or not the proposed segmented design is fabricable. If the total paintbrush loss indicates that the proposed segmented design is not fabricable, the design verification system updates the proposed segmented design based on a gradient of the total paintbrush loss.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: January 5, 2021
    Assignee: X Development LLC
    Inventors: Brian Adolf, Jesse Lu, Martin Schubert