Patents Examined by Syed Gheyas
  • Method and apparatus for repairing a display panel
    Patent number: 9685637
    Abstract: An apparatus and method for repairing a display panel are provided. The apparatus includes a laser emitter that etches a faulty portion of the display panel and a first surrounding portion of the faulty portion by irradiating the faulty portion and the first surrounding portion with a laser and a guide disposed to face the laser emitter and configured to adjust at least one of a temperature of the faulty portion or a temperature of the first surrounding portion.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 20, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joon-Geol Kim
  • Isolated through silicon via and isolated deep silicon via having total or partial isolation
    Patent number: 9673081
    Abstract: Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: June 6, 2017
    Assignee: Newport Fab, LLC
    Inventors: Hadi Jebory, David J. Howard, Marco Racanelli, Edward Preisler
  • Magnetic memory element and magnetic memory
    Patent number: 9659996
    Abstract: According to one embodiment, a magnetic memory element comprises a first magnetic unit, a second magnetic unit, a first insulating unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit includes a plurality of magnetic domains. The second magnetic unit includes a first region and a second region. The first region includes a conductive material. The second region includes an insulating material. At least one of the first region or the second region is magnetic. The first insulating unit is provided between the first magnetic unit and the second magnetic unit. The first electrode and the second electrode are connected to the first magnetic unit. A part of the second magnetic unit and a part of the first insulating unit are provided between the third electrode and a part of the first magnetic unit.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Shimada, Hirofumi Morise, Shiho Nakamura, Tsuyoshi Kondo, Yasuaki Ootera, Michael Arnaud Quinsat
  • Method of forming deep trench and deep trench isolation structure
    Patent number: 9659874
    Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Chiang Kuo, Ying-Hsun Chen, Shih-Chi Kuo, Tsung-Hsien Lee
  • Manufacturing methods for accurately aligned and self-balanced superjunction devices
    Patent number: 9647059
    Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.
    Type: Grant
    Filed: June 8, 2014
    Date of Patent: May 9, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingping Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Semiconductor structure with enhanced contact and method of manufacture the same
    Patent number: 9647115
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Long Chen, Meng-Chun Chang, Sung-Li Wang, Yi-Fang Pai, Yusuke Oniki
  • Silicon nanowire formation in replacement metal gate process
    Patent number: 9647062
    Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita
  • Integration of absorption based heating bake methods into a photolithography track system
    Patent number: 9613801
    Abstract: A method of patterning a layered substrate is provided that includes forming a layer of a block copolymer on a substrate, annealing the layer of the block copolymer to affect microphase segregation such that self-assembled domains are formed, and annealing the layer of the block copolymer a second time to refine or modify the microphase segregation, where one of the annealing steps uses an absorption based heating method.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 4, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Benjamen M. Rathsack
  • Composition for forming N-type diffusion layer, method of forming N-type diffusion layer, and method of producing photovoltaic cell
    Patent number: 9608143
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Grant
    Filed: November 10, 2013
    Date of Patent: March 28, 2017
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Youichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuichiro Adachi, Tetsuya Sato, Keiko Kizawa
  • Semiconductor device
    Patent number: 9601634
    Abstract: A highly reliable semiconductor device which uses an oxide semiconductor film for a backplane is provided. A semiconductor device includes a first conductive film, a first insulating film over the first conductive film, an oxide semiconductor film which is over the first insulating film and overlaps with the first conductive film, a second insulating film over the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film through an opening portion included in the second insulating film. The second insulating film overlaps with a region of the oxide insulating film in which a carrier flows between the pair of second conductive films and overlaps with end portions of the oxide semiconductor film.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Chieko Misawa, Yuka Yokoyama, Hironobu Takahashi, Kenichi Okazaki
  • Method of manufacturing semiconductor device
    Patent number: 9589923
    Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
  • Layer transferring process
    Patent number: 9583341
    Abstract: A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Soitec
    Inventors: Vivien Renauld, Monique Lecomte
  • Method of forming a silicon-carbide device with a shielded gate
    Patent number: 9577073
    Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Semiconductor device and method of manufacturing the same
    Patent number: 9576977
    Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Deung Kak Yoo
  • Method of forming a nanowire
    Patent number: 9564317
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first material layer over a substrate. The first material layer has a sidewall defining a first opening, wherein the first opening has a first shape. The method also includes forming a sacrificial feature within the first opening and the sacrificial feature has a second shape, which is different than the first shape such that there is a cavity between an edge of the sacrificial feature and the sidewall of the first material layer. The method also includes filling in cavity with a second material layer, removing the sacrificial feature to form a second opening, filling in the second opening with a third material layer, removing the second material layer to reveal the cavity and forming a conductive feature within the cavity.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Blandine Duriez, Martin Christopher Holland
  • Thin film transistor, method of manufacturing thin film transistor and flat panel display having the thin film transistor
    Patent number: 9552998
    Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: January 24, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myoung-Geun Cha, Sang-Ho Park, Hyun-Jae Na, Yoon-Ho Khang, Dae-Ho Kim
  • Variable frequency microwave (VFM) processes and applications in semiconductor thin film fabrications
    Patent number: 9548200
    Abstract: Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating mechanism and a variable frequency microwave source. The methods described herein use variable frequency microwave radiation to increased quality and speed of the degas process without damaging the various components.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 17, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Loke Yuen Wong, Ke Chang, Yueh Sheng Ow, Ananthkrishna Jupudi, Glen T. Mori, Aksel Kitowski, Arkajit Roy Barman
  • Method of forming a silicon-carbide device with a shielded gate
    Patent number: 9543414
    Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Self-aligned split gate flash memory
    Patent number: 9536969
    Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsueh Yang, Chung-Chiang Min, Chang-Ming Wu, Shih-Chang Liu
  • Composition for forming P-type diffusion layer, method of forming P-type diffusion layer, and method of producing photovoltaic cell
    Patent number: 9520529
    Abstract: The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Grant
    Filed: November 9, 2013
    Date of Patent: December 13, 2016
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Yoichi Machii, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuichiro Adachi, Tetsuya Sato, Keiko Kizawa