Abstract: A method for manufacturing an organic light-emitting diode (OLED) device includes: forming auxiliary electrodes (2) on a resin layer (1) of an OLED substrate; forming a gas generation layer (4) on the auxiliary electrodes (2); forming an organic light-emitting layer (6) on the gas generation layer (4); placing a receptor substrate (12) on the organic light-emitting layer (6) and scanning auxiliary electrode regions (22) by laser, so that the gas generation layer (4) is decomposed under laser irradiation to release gas, and hence the organic light-emitting layer (6) in the auxiliary electrode regions (22) is transferred to the receptor substrate (12); removing the receptor substrate (12); and forming a cathode (7) on the auxiliary electrodes. The manufacturing process can effectively reduce poor contact between the auxiliary electrodes and the cathode.

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a portion of the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device comprises a workpiece including a conductive feature disposed in a first insulating material and a second insulating material disposed over the first insulating material, the second insulating material having an opening over the conductive feature. A graphene-based conductive layer is disposed over an exposed top surface of the conductive feature within the opening in the second insulating material. A carbon-based adhesive layer is disposed over sidewalls of the opening in the second insulating material. A carbon nano-tube (CNT) is disposed within the patterned second insulating material over the graphene-based conductive layer and the carbon-based adhesive layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure comprised of a low-density oxide material having a density of less than 1.8 g/cm3 on and in contact with the upper surface and the side surfaces of the fin and a sacrificial gate material positioned on and in contact with the upper surface of the low-density oxide material, and forming a sidewall spacer adjacent the sacrificial gate structure. The method further includes removing the sacrificial gate material so as to thereby expose the low-density oxide material, so as to define a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Abstract: A method of detaching a sealing member of a light emitting device which has a substrate, a light emitting element mounted on the substrate and a sealing member that seals the light emitting element, wherein a release layer and/or an air layer is/are provided between the substrate and the sealing member; and the sealing member is detached from the substrate at the release layer and/or the air layer.

Abstract: A substrate processing system for depositing film on a substrate includes a processing chamber defining a reaction volume and including a substrate support for supporting the substrate. A gas delivery system is configured to introduce process gas into the reaction volume of the processing chamber. A plasma generator is configured to selectively generate RF plasma in the reaction volume. A clamping system is configured to clamp the substrate to the substrate support during deposition of the film. A backside purging system is configured to supply a reactant gas to a backside edge of the substrate to purge the backside edge during the deposition of the film.

Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a pattern of an organic light-emitting layer (11); a pattern of an active layer (4a) located in a thin film transistor region and a pattern of an absorbing layer (4b) located in an open region, which are arranged in a same layer, wherein, the pattern of the absorbing layer (4b) is located in a light outgoing direction of the pattern of the organic light-emitting layer (11), and is made of a transparent material having an ultraviolet absorbing function.

Abstract: A display device includes a substrate, a first electrode on the substrate, a pixel defining layer on the substrate, the pixel defining layer having an opening exposing the first electrode, a metal layer on the pixel defining layer, a light emission layer on the first electrode exposed by the opening, and a second electrode on the light emission layer in the opening. The metal layer contacts the second electrode.

Abstract: A display panel and a display device are provided, and the display panel comprises a GOA circuit; a first conducting wire and a second conducting wire are disposed in a region outside the GOA circuit; an insulating layer is disposed between the first conducting wire and the second conducting wire; and the first conducting wire, the insulating layer and the second conducting wire form a first capacitor. The display panel can protect the internal signal lines of the GOA circuit and the display panel, and increase the antistatic ability of the display panel and the yield of products.

Abstract: A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package.

Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.

Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Abstract: Disclosed is a method for fabricating an array substrate, comprising: forming a pattern layer comprising a gate and a gate connection on a substrate; sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection; sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: Provided is a process for modifying the chemical composition of a surface region of a material, employing rapid thermal processing (RTP) conditions.

Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.