Abstract: The present invention provides a sample stack structure with multiple layers. The sample stack structure has at least a substrate, an adhesive layer and a target layer. The target layer is directly sandwiched between the substrate and the adhesive layer.

Abstract: First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C.

Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.

Abstract: A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.

Abstract: To provide a semiconductor device in which the threshold value is controlled. Furthermore, to provide a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as a transistor is miniaturized can be suppressed. The semiconductor device includes a first semiconductor film, a source electrode and a drain electrode electrically connected to the first semiconductor film, a gate insulating film, and a gate electrode in contact with the gate insulating film. The gate insulating film includes a first insulating film and a trap film, and charge is trapped in a charge trap state in an interface between the first insulating film and the trap film or inside the trap film.

Abstract: A method of manufacturing a light-emitting device includes forming a wave length conversion portion on a light-emitting element. The light emitting device includes a light-emitting element which emits light of a predetermined wavelength and a wavelength conversion portion which includes a fluorescent substance which is excited by the light emitted from the light-emitting element so as to emit fluorescence of a wavelength different from the predetermined wavelength, which wavelength conversion portion is formed by including the fluorescent substance, a layered silicate mineral, and an organometallic compound.

Abstract: A liquid crystal display includes: a first substrate, a gate line and a data line disposed on the first substrate, a thin film transistor connected to the gate line and the data line, a first passivation layer disposed on the thin film transistor, a first electrode disposed on the first passivation layer, a second passivation layer disposed on the first electrode and a second electrode disposed on the second passivation layer. A first edge of the first electrode and a second edge of the second passivation layer have substantially the same plane shape as each other, and the second edge of the second passivation layer protrudes more than the first edge of the first electrode.

Abstract: A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.

Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: Provided are a reaction tube, a substrate processing apparatus, and a method of manufacturing a semiconductor device capable of suppressing a non-uniform distribution of a gas in a top region to improve the flow of the gas and film uniformity within and between substrate surfaces. The reaction tube has a cylindrical shape, accommodates a plurality of substrates stacked therein, and includes a cylindrical portion and a ceiling portion covering an upper end portion of the cylindrical portion, the ceiling portion having a substantially flat top inner surface. A thickness of a sidewall of the ceiling portion is greater than that of a sidewall of the cylindrical portion.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a conductive layer, a conductive architecture and a dielectric layer. The conductive layer defines adjacent first openings. The conductive architecture surrounds a portion of the conductive layer between the first openings. The dielectric layer separates the conductive layer and the conductive architecture.

Abstract: Networks of semiconductor structures with fused insulator coatings and methods of fabricating networks of semiconductor structures with fused insulator coatings are described. In an example, a method of fabricating a semiconductor structure involves forming a mixture including a plurality of discrete semiconductor nanocrystals. Each of the plurality of discrete semiconductor nanocrystals is discretely coated by an insulator shell. The method also involves adding a base to the mixture to fuse the insulator shells of each of the plurality of discrete nanocrystals, providing an insulator network. Each of the plurality of discrete semiconductor nanocrystals is spaced apart from one another by the insulator network. The base one such as, but not limited to, LiOH, RbOH, CsOH, MgOH, Ca(OH)2, Sr(OH)2, Ba(OH)2, (Me)4NOH, (Et)4NOH, or (Bu)4NOH.

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region. The method includes forming etching selection regions in portions of the active region that are exposed after forming the preliminary trenches. The method includes forming trenches by removing the etching selection regions. Moreover, the method includes forming a stressor in the trenches. Related apparatuses are also provided.

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract: A (000-1) C-plane of an n? type silicon carbide substrate having an off-angle ? in a <11-20> direction is defined as a principal plane, and a periphery of a portion of this principal surface layer defined as an alignment mark is selectively removed to leave the convex-shaped alignment mark. The alignment mark has a cross-like plane shape such that two rectangles having longitudinal dimensions tilted by 45 degrees relative to the <11-20> direction are orthogonal to each other. When a film thickness of a p? type epitaxial layer is Y; a width of the alignment mark parallel to the principal surface of the n? type silicon carbide substrate is X; and an off-angle of the n? type silicon carbide substrate is ?, an epitaxial layer is formed on an upper surface of the alignment mark such that Y?X·tan ? is satisfied.

Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).

Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.