Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.
Abstract: A surface side is irradiated with an SF6 gas plasma to etch a semiconductor wafer which has been peeled off in street portions, and divide the semiconductor wafer into a plurality of individual semiconductor chips. A removing agent is subsequently supplied from the surface side. At that time, it is preferable that the semiconductor wafer divided into the plurality of chips is rotated at high speed. Accordingly, a mask material layer remaining on the surface is removed by the removing agent. Moreover, the removing agent is preferably an organic solvent, and more preferably, methyl ethyl ketone, ethanol, and ethyl acetate, or a combination of these.
Abstract: Quantum dot semiconductor nanoparticle compositions that incorporate ions such as zinc, aluminum, calcium, or magnesium into the quantum dot core have been found to be more stable to Ostwald ripening. A core-shell quantum dot may have a core of a semiconductor material that includes indium, magnesium, and phosphorus ions. Ions such as zinc, calcium, and/or aluminum may be included in addition to, or in place of, magnesium. The core may further include other ions, such as selenium, and/or sulfur. The core may be coated with one (or more) shells of semiconductor material. Example shell semiconductor materials include semiconductors containing zinc, sulfur, selenium, iron and/or oxygen ions.
Type:
Grant
Filed:
October 11, 2019
Date of Patent:
February 2, 2021
Assignee:
Nanoco Technologies Ltd.
Inventors:
Paul Anthony Glarvey, James Harris, Steven Daniels, Nigel Pickett, Arun Narayanaswamy
Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
Type:
Grant
Filed:
March 16, 2020
Date of Patent:
January 19, 2021
Assignee:
Infineon Technologies AG
Inventors:
Edmund Riedl, Wu Hu Li, Alexander Heinrich, Ralf Otremba, Werner Reiss
Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
Type:
Grant
Filed:
March 16, 2020
Date of Patent:
January 12, 2021
Assignee:
Infineon Technologies AG
Inventors:
Edmund Riedl, Wu Hu Li, Alexander Heinrich, Ralf Otremba, Werner Reiss
Abstract: To provide a semiconductor device 100 including a semiconductor element with a less warped chip. A semiconductor device manufacturing method include: bonding a rear surface of a chip having electrodes on both sides thereof to a front surface of a substrate; providing, to the front surface of the substrate to which the chip is bonded, a plating protective film having an opening at a position which is on the front surface of the chip and corresponds to an electrode at which plating is to be formed, after the bonding; plating the electrode of the chip after the providing; and removing the plating protective film from the substrate, after the plating.
Abstract: A growth layer having a growth surface with protruding domains is described. The protruding domains can be separated by a substantially flat growth surface located between the protruding domains. A protruding domain can include an internal region that can be filled with a gas and/or can be partially or completely filled with one or more materials that differ from the material of the growth layer, which forms an outer surface of each of the protruding domains.
Abstract: A display device comprises: a display panel in which a plurality of pixels are arranged in a matrix form, wherein the plurality of pixels include a plurality of first pixels and a plurality of second pixels arrayed at a pitch different from an array pitch of the plurality of first pixels, and a number of the plurality of first pixels is different from a number of the plurality of second pixels.
Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.
Type:
Grant
Filed:
October 10, 2019
Date of Patent:
January 5, 2021
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Kangguo Cheng, Ekmini A. De Silva, Juntao Li, Yi Song, Peng Xu
Abstract: Reference oscillators are ubiquitous in timing applications generally, and in modern wireless communication devices particularly. Microelectromechanical system (MEMS) resonators are of particular interest due to their small size and potential for integration with other MEMS devices and electrical circuits on the same chip. In order to support their use in high volume low cost applications it would be beneficial for MEMS designers to have MEMS resonator designs and manufacturing processes that whilst employing low cost low resolution semiconductor processing yield improved resonator performance thereby reducing the requirements of the oscillator circuitry. It would be further beneficial for the oscillator circuitry to be able to leverage the improved noise performance of differential TIAs without sacrificing power consumption.
Type:
Grant
Filed:
November 7, 2018
Date of Patent:
December 29, 2020
Assignees:
Socovar, Societe en Commandite, TRansfer Plus, Sciete en Commandite
Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method includes providing a semiconductor substrate, forming a redistribution line on a top surface of the semiconductor substrate, and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. The forming a redistribution line includes a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line. An average grain size of the second segment of the redistribution line is less than an average grain size of the first segment of the redistribution line.
Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, and a staircase structure on one side of the memory stack. The 3D memory device also includes a staircase contact in the staircase structure and a plurality of dummy source structures each extending vertically through the staircase structure. The plurality of dummy source structures surround the staircase contact.
Abstract: An electronic component includes a wiring substrate, surface mount devices mounted on a front surface of the wiring substrate, and a shield plate fixed on a side adjacent to top surfaces of the surface mount devices. The shield plate includes a magnetic ceramic sintered sheet and a first metal film. The magnetic ceramic sintered sheet includes a first main surface and a second main surface. The first metal film is disposed on the first main surface of the magnetic ceramic sintered sheet.
Abstract: In fabricating a radio frequency (RF) switch, a heat spreader is provided and a heating element is deposited. A thermally conductive and electrically insulating material is deposited over the heating element. The heating element and the thermally conductive and electrically insulating material are patterned, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A layer of an upper dielectric is deposited. A conformability support layer is optionally deposited over the upper dielectric and the thermally conductive and electrically insulating material. A phase-change material is deposited over the optional conformability support layer and the underlying upper dielectric and the thermally conductive and electrically insulating material.
Type:
Grant
Filed:
August 30, 2019
Date of Patent:
December 8, 2020
Assignee:
Newport Fab, LLC
Inventors:
Gregory P. Slovin, Jefferson E. Rose, David J. Howard, Michael J. DeBar, Nabil El-Hinnawy
Abstract: A semiconductor package includes a second leadframe assembly stacked above a first leadframe assembly, each leadframe assembly including a die pad, a plurality of leads and a semiconductor die attached to the die pad and electrically connected to the leads. An electrically insulative spacer separates the first and the second leadframe assemblies from one another. A mold compound embeds part of the first leadframe assembly, part of the second leadframe assembly and the electrically insulative spacer.
Abstract: Embodiments of a three-dimensional (3D) memory device are provided. The 3D memory device includes a substrate, a memory stack with interleaved conductive layers and dielectric layers over the substrate, an array of channel structures each extending vertically through the memory stack, and a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures. At least one of the plurality of contact hole structures is surrounded by a plurality of the channel structures of nominally equal lateral distances to the respective contact hole structure.
Abstract: A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property.