Abstract: A device includes a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile. The device further includes a contact plug electrically connected to the protrusion.

Abstract: A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.

Abstract: According to some embodiments in this application, a method for making a JFET device is disclosed in the following steps: forming a substrate; performing ion implantation on the first region and the second region of the substrate to form a deep N-type well, wherein the deep N-type well is formed with at least two sub-wells region; forming a field oxide in the second region; forming a P-type well in one side of the sub-well in the deep N-type well; performing P-type ion implantation on the third region and the fourth region to respectively form a first P-type heavily doped region and a second P-type heavily doped region; and performing N-type ion implantation on the fifth region, the sixth region, and the seventh region to respectively form a first N-type heavily doped region, a second N-type heavily doped region, and a third N-type heavily doped region.

Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

Abstract: A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol. %. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed.

Abstract: A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

Abstract: A thin film transistor (TFT) and a method of manufacturing same are provided. A photoresist layer is dry-etched to form a tunnel before an active layer is formed, wherein a bottom of the tunnel is a copper trace layer. After that, two edges of the photoresist layer are aligned with two edges of the copper trace layer. Therefore, the photoresist layer won't protrude over an amorphous silicon layer to block the etching gas from etching the amorphous silicon layer. As a result, an aperture ratio of the TFT is increased, and quality of the TFT is improved. By forming an oxidation protective layer on the tunnel, the copper trace layer is prevented from being reacted with the etching gas to form a compound. Therefore, metals or compounds on the tunnel can be completely etched, and quality of the TFT is further improved.

Abstract: A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.

Abstract: A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol. %. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

Abstract: A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.

Abstract: An integrated circuit includes one or more bipolar transistors, each including a first dielectric layer located over a semiconductor layer having a first conductivity type, the dielectric layer including an opening. A second dielectric layer is located between the first dielectric layer and the semiconductor layer. The second dielectric layer defines a first recess between the first dielectric layer and the semiconductor substrate at a first side of the opening, and a second recess between the first dielectric layer and the semiconductor substrate at a second opposite side of the opening. A first doped region of the semiconductor layer is located under the opening, the first doped region having a different second conductivity type and a first width. A second doped region of the semiconductor layer is also under the opening, the second doped region having the second conductivity type and underlying the first recess and the second recess.

Abstract: The invention provides a structure of an emitter layer and a base layer that reduces the influence of a conduction band energy barrier generated at an interface between the emitter layer and the base layer on power amplifier characteristics for a GaAs HBT using InGaAs grown by pseudomorphic growth in the base layer. In the first invention, InGaP having a CuPt-type ordering is used in the emitter layer. In the second invention, a p-type impurity concentration of an InGaAs base layer grown by pseudomorphic growth is less in an emitter layer side portion than in a collector layer side portion.

Abstract: Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Abstract: This disclosure provides a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor and a preparation method thereof. An InGaP material has characteristics of a high carrier mobility of the InP material and a forbidden band width of the GaP material, so that the present disclosure employs the N-type In1-xGaxP layer as the collector to improve the frequency and power characteristics of the device, and realize the system integration of terahertz band chips. Further, the present disclosure utilizes the characteristics of the above materials and takes an advantages of “energy band engineering”, uses the In1-xGaxP (x=0-1) is used as the material of the collector of the SiGe-HBT, the composition molar ratio X of In and Ga is appropriately selected, such that the materials SiGe of the collector and the sub-collector have the same lattice constant, so as to effectively improve interface characteristics of InGaP and SiGe materials.

Abstract: Vertical bipolar junction transistors (VBJTs), each with one or more resistors connected in a circuit in different circuit configurations, are disclosed. The VBJT has an emitter substructure that includes an emitter layer, a collector, an intrinsic base, one or more doped epitaxy regions, and one or more resistors. The intrinsic base, the doped epitaxy region(s), and the resistor(s) are stacked upon one another in a channel between the emitter layer and the collector. Various circuit configurations and structures are described including a common-collector circuit, a common-emitter circuit, and an emitter-degenerate circuit. Methods of making these configuration/structures are disclosed.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first and second epitaxial layers, and first and second semiconductor layers. The second epitaxial layer is disposed on the first epitaxial layer. The first semiconductor layer extends from above the second epitaxial layer to a top surface of the second epitaxial layer. A vertically extending region of the first semiconductor layer has a body portion and an extending portion extending from a bottom end of the body portion to the second epitaxial layer. A width of the body portion is greater than a width of the extending portion. The second semiconductor layer is disposed on the second epitaxial layer, and laterally surrounds the vertically extending region of the first semiconductor layer. A portion of the second semiconductor layer extends between and overlaps with the body portion of the first semiconductor layer and the second epitaxial layer.