Abstract: A method for forming a light emitting element pattern according to an embodiment of the inventive concept includes forming a pattern layer having an opening on a target material, forming a light emitting element pattern on the target material in correspondence to the opening, and removing the pattern layer. Here, the pattern layer includes a first pattern layer disposed on the target material, a second pattern layer disposed on the first pattern layer, and a third pattern layer disposed on the second pattern layer. The second pattern layer has an undercut portion recessed from edges of the third pattern layer.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

Abstract: A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The method may further include forming a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate overlying the asymmetric channel.

Abstract: A method of manufacturing an insulated-gate semiconductor device, includes: digging a gate trench and a dummy trench; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; exposing an upper portion of the dummy electrode and selectively forming an insulating film for testing so as to cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport, region.

Abstract: The present disclosure provides a semiconductor structure, including: a transistor, including a gate structure and a source/drain structure; a source/drain contact, disposed over the source/drain structure; a gate contact, disposed over the gate structure; and a conductive bridge, disposed over the transistor, wherein the conductive bridge overlaps the source/drain contact from a top view perspective and electrically connecting the gate contact. The present disclosure also provides a method for forming the same.

Abstract: The present disclosure provides a film material and a display device, and relates to the field of display technology. The film material includes a base material and a functional film layer arranged on the base material, in which the base material includes an active region and an auxiliary region surrounding the active region, the functional film layer covering the active region, and not completely covering the auxiliary region. The film material provided by the present disclosure is applied into a display device.

Abstract: The present invention includes a method of fabricating an integrated RF power condition capacitor with a capacitance greater than or equal to 1 of and less than 1 mm2, and a device made by the method.

Abstract: A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.

Abstract: Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

Abstract: A semiconductor element includes an element body, a surface protective film and an electrode. The element body has a front surface and a side surface connected to the front surface. The surface protective film is supported on the front surface of the element body. The surface protective film has a cutout portion recessed inward from an outer edge of the surface protective film as viewed in a thickness direction of the element body. The electrode is disposed in the cutout portion and electrically connected to the element body. The element body has a ledge protruding with respect to the side surface in a direction perpendicular to the thickness direction. The ledge is adjacent to an opening of the cutout portion as viewed in the thickness direction.

Abstract: Compositions, systems, and methods are described for implanting silicon and/or silicon ions in a substrate, involving generation of silicon and/or silicon ions from corresponding silicon precursor compositions, and implantation of the silicon and/or silicon ions in the substrate.

Abstract: A method for thinning a substrate is provided. The method includes at least the following steps. A substrate is disposed on a carrying surface of a chuck, where a first liquid supply unit surrounds the chuck to form a frame of the chuck, and an outlet of the first liquid supply unit is disposed aside the carrying surface of the chuck. A first liquid flows from a bottom of the frame to the outlet and discharges to fill a gap between the substrate and the carrying surface of the chuck. The substrate is thinned during the gap is filled.

Abstract: Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Abstract: A pixel structure includes a transmissive area and a reflective area. The pixel structure includes a first transparent electrode, a second transparent electrode, a reflective electrode, a first switching element, and a second switching element. The first transparent electrode has a first portion and a second portion connected to each other. The first portion is disposed in the reflective area, and the second portion is disposed in the transmissive area and is narrower than the first portion. The second transparent electrode is disposed in the transmissive area. The reflective electrode is stacked on the first portion of the first transparent electrode and is isolated from the second transparent electrode. The first switching element is disposed in the reflective area and is electrically connected to the first transparent electrode. The second switching element is disposed in the reflective area and is electrically connected to the second transparent electrode.

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.

Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.