Patents Examined by Syed I Gheyas
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Patent number: 11031517Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a compound thin film, which includes configuring an electrodeposition circuit by connecting an electrolytic solution, which is manufactured by mixing a predetermined precursor with a solvent, and an electrochemical cell, which includes a working electrode in a form of an electrode at which a specific pattern is patterned on a predetermined substrate, to a voltage application device or a current application device, and applying a reduction voltage or current to the working electrode using the voltage application device or the current application device, and selectively electrodepositing a thin film in some region of the electrode along a shape of the electrode at which the specific pattern is patterned.Type: GrantFiled: August 24, 2018Date of Patent: June 8, 2021Assignee: Korea Institute of Science and TechnologyInventors: Doh-Kwon Lee, Jangmi Lee, Inho Kim, Jeung-hyun Jeong
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Patent number: 11024576Abstract: A semiconductor package includes a leadframe including a sensor coil between sensor coil leads and further including a plurality of die leads physically and electrically separated from the sensor coil, and a semiconductor die over the leadframe with die contacts electrically connected to the die leads. The semiconductor die includes a sensor operable to detect magnetic fields created by electrical current through the sensor coil, the semiconductor die operable to output a signal representative of the detected magnetic fields via the die leads. The semiconductor package further includes a dielectric underfill filling a gap between the sensor coil and the semiconductor die, and a dielectric mold compound covering the sensor coil and the dielectric underfill and at least partially covering the semiconductor die and the die leads.Type: GrantFiled: December 31, 2019Date of Patent: June 1, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Alan West, Byron Lovell Williams, Thomas Dyer Bonifield
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Patent number: 11018169Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a capacitor. The capacitor is over a substrate and includes a first electrode having a plurality of first electrode layers that are vertically stacked over one another. The plurality of first electrode layers respectively contact an adjacent first electrode layer in a plurality of first connection regions. A second electrode including a plurality of second electrode layers that are vertically stacked over one another. The plurality of second electrode layers respectively contact an adjacent second electrode layer in a plurality of second connection regions. The plurality of second electrode layers are respectively stacked between adjacent ones of the plurality of first electrode layers. A capacitor dielectric structure separates the plurality of first electrode layers and the plurality of second electrode layers.Type: GrantFiled: August 19, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yimin Huang
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Patent number: 11018251Abstract: A semiconductor device includes a semiconductor body; first and second electrodes provided on back and front surfaces of the semiconductor body, respectively; a third electrode provided on the front surface; and a control electrode disposed inside a trench on the front surface side, and electrically connected to the third electrode. The third electrode is electrically insulated from the semiconductor body and the second electrode. The control electrode is placed between the semiconductor body and the second electrode, and is electrically insulated from the semiconductor body and the second electrode. The control electrode continuously extends inside the trench without branching. The control electrode includes first and second portions. The first portion extends in a first direction parallel to the front surface of the semiconductor body, and the second portion extends in a second direction parallel to the front surface of the semiconductor body and crossing the first direction.Type: GrantFiled: August 19, 2019Date of Patent: May 25, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Toshifumi Nishiguchi
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Patent number: 11018219Abstract: The invention discloses a P-type MOSFET, a channel region consisting of an N-well is formed in the semiconductor substrate covered with a gate structure; the N-well is formed by overlaying an annealed phosphorus-implanted region, an annealed first arsenic-implanted region and an annealed second arsenic-implanted region, and the first arsenic-implanted region and the second arsenic-implanted region are overlaid to form a threshold voltage regulation region; the implantation depth of the first arsenic-implanted region is greater than that of the second arsenic-implanted region; and an amorphous layer is formed by the first arsenic-implanted region on the semiconductor substrate to improve the implantation uniformity of the second arsenic-implanted region and to decrease the peak surface doping concentration of the second arsenic-implanted region located on the surface of the semiconductor substrate. The invention further discloses a method for manufacturing a P-type MOSFET.Type: GrantFiled: December 5, 2019Date of Patent: May 25, 2021Assignee: Shanghai Huali Integrated Circuit CorporationInventor: Zhonghua Li
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Patent number: 11011630Abstract: A semiconductor wafer is provided, which has a silicon wafer, a reaction suppressing layer, a stress generating layer and an active layer, the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer being disposed in an order of the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer, where the reaction suppressing layer is a nitride crystal layer that suppresses reaction between silicon atoms and group-III atoms, the stress generating layer is a nitride crystal layer that generates compressive stress, the active layer is a nitride crystal layer in which an electronic device is formed, and the semiconductor wafer further has, between the silicon wafer and the reaction suppressing layer, a SiAlN layer having silicon atoms, aluminum atoms and nitrogen atoms as main constituent atoms.Type: GrantFiled: May 29, 2019Date of Patent: May 18, 2021Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki Yamamoto, Takenori Osada
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Patent number: 10991659Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.Type: GrantFiled: December 5, 2019Date of Patent: April 27, 2021Assignee: Apple Inc.Inventors: Flynn P. Carson, Jun Chung Hsu, Meng Chi Lee, Shatki S. Chauhan
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Patent number: 10985165Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: August 19, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Si-Woo Lee, Kyuseok Lee, Sangmin Hwang
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Patent number: 10978563Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first insulator; a first conductor over the first insulator; a second insulator over the first conductor; a first oxide over the second insulator; second and third conductors over the first oxide; a third insulator over the second and third conductors; a second oxide over the first oxide and between the second and third conductors; a fourth insulator over the second oxide; a fourth conductor over the fourth insulator; a fifth insulator in contact with the third insulator and the second oxide; a sixth insulator in contact with the first, second, third, and fifth insulators, and the second oxide; and a seventh insulator in contact with the fourth and sixth insulators, the second oxide, and the fourth conductor. The first, sixth, and seventh insulators each contain a silicon nitride. The fifth insulator contains an aluminum oxide.Type: GrantFiled: November 27, 2019Date of Patent: April 13, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Katsuaki Tochibayashi, Ryota Hodo, Shunpei Yamazaki
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Patent number: 10971456Abstract: An electronic component includes a multilayer body including a first insulator and a second insulator having a higher resistivity than the first insulator, metal conductors each positioned between the first insulator and the second insulator and including a predetermined end surface positioned at least near an end surface of the multilayer body, plating films each provided on the predetermined end surface of the metal conductor in a state extending out in a direction covering an end surface of the first insulator by a larger distance than in a direction covering an end surface of the second insulator, and an outer conductor provided on the outer sides of the plating films and electrically connected to the metal conductor through the plating films.Type: GrantFiled: September 19, 2019Date of Patent: April 6, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Ryosuke Washida, Jyunichi Nanjyo, Narimichi Makino
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Patent number: 10937647Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.Type: GrantFiled: February 11, 2019Date of Patent: March 2, 2021Assignee: FUJITSU LIMITEDInventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
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Patent number: 10937808Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.Type: GrantFiled: August 8, 2019Date of Patent: March 2, 2021Assignee: SK HYNIX INC.Inventors: Jae Gil Lee, Ju Ry Song, Hyangkeun Yoo, Se Ho Lee
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Patent number: 10930615Abstract: Semiconductor device includes: substrate having substrate main surface and substrate rear surface facing opposite sides to each other in first direction, and substrate side surface facing in second direction orthogonal to the first direction; wiring layer having main surface electrode covering a portion of the substrate main surface, and side surface electrode connected to the main surface electrode and covering a portion of the substrate side surface; semiconductor element electrically connected to the main surface electrode and mounted on the substrate to face the substrate main surface; and sealing resin having resin side surface facing in the same direction as the substrate side surface, and covering the semiconductor element and the main surface electrode, wherein the side surface electrode has side exposed surface exposed from the sealing resin and facing in the same direction as the substrate side surface, the side exposed surface being flush with the resin side surface.Type: GrantFiled: May 8, 2019Date of Patent: February 23, 2021Assignee: ROHM CO., LTD.Inventor: Taro Hayashi
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Patent number: 10923592Abstract: A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.Type: GrantFiled: June 4, 2019Date of Patent: February 16, 2021Assignee: pSemi CorporationInventors: Abhijeet Paul, Simon Edward Willard, Alain Duvallet
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Patent number: 10916473Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: GrantFiled: October 17, 2019Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
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Patent number: 10916681Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: GrantFiled: February 8, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-Joon Yoon, Dae-Young Moon, Jeong-Hwan Jang, Yongjo Park, Duk-Kyu Bae
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Patent number: 10916441Abstract: A surface side is irradiated with an SF6 gas plasma to etch a semiconductor wafer which has been peeled off in street portions, and divide the semiconductor wafer into a plurality of individual semiconductor chips. A removing agent is subsequently supplied from the surface side. At that time, it is preferable that the semiconductor wafer divided into the plurality of chips is rotated at high speed. Accordingly, a mask material layer remaining on the surface is removed by the removing agent. Moreover, the removing agent is preferably an organic solvent, and more preferably, methyl ethyl ketone, ethanol, and ethyl acetate, or a combination of these.Type: GrantFiled: August 13, 2019Date of Patent: February 9, 2021Assignee: FURUKAWA ELECTRIC CO., LTD.Inventors: Tomoaki Uchiyama, Akira Akutsu, Hirotoki Yokoi
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Patent number: 10910525Abstract: Quantum dot semiconductor nanoparticle compositions that incorporate ions such as zinc, aluminum, calcium, or magnesium into the quantum dot core have been found to be more stable to Ostwald ripening. A core-shell quantum dot may have a core of a semiconductor material that includes indium, magnesium, and phosphorus ions. Ions such as zinc, calcium, and/or aluminum may be included in addition to, or in place of, magnesium. The core may further include other ions, such as selenium, and/or sulfur. The core may be coated with one (or more) shells of semiconductor material. Example shell semiconductor materials include semiconductors containing zinc, sulfur, selenium, iron and/or oxygen ions.Type: GrantFiled: October 11, 2019Date of Patent: February 2, 2021Assignee: Nanoco Technologies Ltd.Inventors: Paul Anthony Glarvey, James Harris, Steven Daniels, Nigel Pickett, Arun Narayanaswamy
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Patent number: 10910342Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.Type: GrantFiled: December 8, 2017Date of Patent: February 2, 2021Assignees: IMEC VZW, UNIVERSITEIT GENTInventors: Maria Op de Beeck, Bjorn Vandecasteele
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Patent number: 10903238Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.Type: GrantFiled: January 23, 2020Date of Patent: January 26, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Katsumi Yamamoto, Keisuke Kikutani