Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

Abstract: A drive system according to an aspect of the embodiment includes a first phase estimation unit, a second phase estimation unit, a state determination unit, and a drive control unit. The first phase estimation unit generates a first phase obtained by estimating a phase of a rotor on the basis of an initial phase at a startup stage of the synchronous motor. The second phase estimation unit generates a second phase obtained by estimating the phase of the rotating rotor on the basis of the operation state of the synchronous motor. The state determination unit determines the operation state of the synchronous motor. The drive control unit controls the driving of the synchronous motor by using any one of the first phase and the second phase according to the determination result of the operation state of the synchronous motor.

Abstract: A control device includes a control section configured to control opening and closing of a structure. the control section controls an opening operation or a closing operation of the structure to match an operation direction of the structure obtained by a sensor provided to the structure, and the control section further controls the closing operation of the structure until the structure is fully closed when the operation direction of the structure obtained by the sensor is a closing direction, and controls the opening operation of the structure until the structure is fully opened when the operation direction of the structure obtained by the sensor is an opening direction.

Abstract: A system for designing a robot for performing a specified function includes a library, a robot design server, and a robot data server. The library stores data about modules and accessories for a robot and has at least unique IDs, dimensions, and firmware for operation of each module and accessory. The robot design server receives a set of functions and requirements of the new robot, finds a set of modules or accessories which match at least one of the set of functions and requirements, performs a set of validation tests against a set of criteria, identifies at least one design which passed the set of validation tests, and generates a list of modules and accessories and their unique IDs of a selected design and a connection map for the selected design. The robot data server downloads to the assembled robot the data and metadata of its modules and accessories.

Abstract: An electronic fuse based-protection circuit system, including a plurality of electronic fuse based-protection circuits, where each electronic fuse based-protection circuit is electrically connected to a power supply and a load through an input terminal and an output terminal respectively and includes a sampling resistor, a MOSFET switch, and a logic control branch circuit. The sampling resistor is electrically connected to the input terminal and has a sampling terminal. The MOSFET switch is electrically connected to the sampling terminal and the output terminal. The logic control branch circuit obtains a sampling voltage of the sampling resistor between the input terminal and the sampling terminal and an on-off judging voltage by amplifying the sampling voltage. When the on-off judging voltage is greater than a reverse-bias voltage of the logic control branch circuit, an off signal is then transmitted to the MOSFET switch, to turn off the MOSFET switch.

Abstract: An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

Abstract: An ammonium acetate selected from the group of pentylammonium acetate, phenylethylammonium acetate, 2-([1,1?-biphenyl]-4-yl) ethan-1-amine acetate, butanammonium acetate, hexylammonium acetate, octylammonium acetate, phenylbutanammonium acetate, and any combination thereof, is used to modify a perovskite layer in a perovskite solar cell. A perovskite solar cell includes a perovskite layer and an interface modification layer that is in contact with the perovskite layer and includes at least one ammonium acetate provided herein. A method of preparing the inverted perovskite solar cell.

Abstract: A slim solar module is proposed. It comprises a solar laminate comprising plural solar cells interposed between front and rear cover sheets, a frame enclosing the solar laminate and at least one reinforcement strut arranged at a rear surface of the solar laminate. A ratio between a frame surface and a frame thickness shall be between 45000 and 70000. For example, the frame may have a thickness of less than 35 mm. Specifically, the frame may have a length of 1665 mm, a width of 991 mm and a thickness of 30 mm. Due to the reduced thickness, the solar module has a reduced volume being beneficial during transport to a destination location. However, the thickness has been optimized to, with the reinforcement struts, still providing for sufficient mechanical stability for the solar module.

Abstract: Braking a power tool motor based on a phase voltage of the motor. The power tool includes a motor and a power source providing operating power to the motor. A power switching network is between the power source and the motor to drive the motor. An actuator is operable to provide an input. An electronic controller is connected to the actuator and the power switching network. The electronic controller is configured to receive an indication related to initiating braking of the motor, control the power switching network to allow the motor to coast, monitor a phase voltage of the motor, determine whether the phase voltage of the motor is equal to or less than a phase voltage threshold, and control, in response to the phase voltage of the motor being equal to or less than the phase voltage threshold, the power switching network to brake the motor.

Abstract: In order to relieve the stress on the substrates in a 3D stacked electronic assembly, a substrate frame is divided into a plurality of frame sections that are separated by spaces between the frame sections. These separations allow the substrates to expand/contract in response to temperature variations and other environmental conditions, and generally allow the substrates to move in one or more axial directions. The separations between the substrate portions are design-specific for each substrate design. The placement of IC packages on either side of the substrate is analyzed to identify areas of maximal warpage through physical measurements, physical model simulations, or using a trained neural network. The spaces in the substrate frame are then be placed next to or aligned with the areas of maximal warpage to reduce the stress on the substrate.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: The invention is directed at an electric power converter, such as an electric motor drive for driving an electric motor. The converter includes a cooling system with a heat sink for dissipating thermal energy generated by the converter and with coolant flow means for cooling the heat sink, first measuring means for measuring the coolant inlet temperature, second measuring means for measuring the heat sink temperature, estimating means for estimating the thermal energy transferred to the heat sink, wherein the converter is provided for estimating the thermal resistance of the heat sink based on the measured temperatures and the estimated thermal energy transferred to the heat sink, for comparing the estimated thermal resistance to reference values and for outputting a signal, if the difference between the estimated thermal resistance and the reference values exceeds a threshold value. The invention is also directed at a method for operating the electric power converter.

Abstract: A real-time clock module coupled to a memory device includes: a timing circuit configured to measure a time to generate time data; a first interface circuit configured to function as a master interface for the memory device; a power supply circuit configured to supply a power supply voltage to the memory device; and a control circuit configured to write, to the memory device, target time data corresponding to at least a part of time digits of the time data via the first interface circuit after the supply of the power supply voltage to the memory device is started, and to stop the supply of the power supply voltage after the target time data is written.

Abstract: A fan controller for a ceiling fan is provided. The fan controller includes one or more switching devices configured to selectively couple the ceiling fan to a power source. The fan controller further includes a power meter circuit and one or more control devices. The one or more control devices are configured to obtain, via the power meter circuit, data indicative of power consumption of a fan motor of the ceiling. The one or more control devices are configured to determine the fan motor is configured in a first mode of a plurality of modes for the fan motor based, at least in part, on the data indicative of power consumption. The one or more control devices are configured to provide a notification to manipulate an input device on the ceiling fan to switch the fan motor from the first mode to a second mode of the plurality of modes.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Abstract: A display panel includes a cover window, an ink layer formed with a multi-layer structure on a rear surface of the cover window and directly adhered to a middle frame, and an adhesive layer disposed on the rear surface of the cover window and overlapping with the ink layer, and at least one layer of the multi-layer structure of the ink layer includes a conductive material. An electric charge generated by the cover window is distributed to the middle frame via the ink layer and discharged by the middle frame to prevent a shift phenomenon, a green phenomenon, or both in the display panel.