Abstract: A memory device includes a memory cell array including a plurality of memory cells, a sub word line driver block including a plurality of sub word line drivers configured to output word line signals, which are respectively provided to the plurality of memory cells, and a row decoder configured to generate word line enable signals, which are respectively provided to the plurality of memory cells. Each of the memory cells includes a cell transistor including dual gates, and a capacitor connected to the cell transistor. A word line enable signal applied by the row decoder is connected to one of the dual gates.

Abstract: A superconducting rotating machine, including: a stator that has a tubular stator iron core and stator windings wound around the stator iron core and generates a rotating magnetic field; a superconducting rotor having: a superconducting squirrel-cage winding that is held rotatably with the rotating magnetic field of the stator on an inner peripheral side and has one or more rotor bars and end rings each made of a superconducting material; and a rotor iron core that has a plurality of slots to accommodate the rotor bars; a pulse voltage output unit that outputs a pulse voltage to shift the superconducting squirrel-cage winding to a magnetic flux flow state; a drive voltage output unit that applies a drive voltage to the stator windings to rotationally drive the superconducting rotor, wherein the pulse voltage output from the pulse voltage output unit is superimposed on the drive voltage.

Abstract: A system for power delivery network (“PDN”) isolation includes a multi-layer printed circuit board (“PCB”) in which a power distribution layer has a root conductive region and two or more branch conductive regions fanning out from the root conductive region. Each branch conductive region is insulated from other branch conductive regions by a non-conductive region. Each branch conductive region has at least one power delivery connection. Each of various electronic circuits mounted on the PCB and sharing the same PDN may be shorted to one of the branch conductive regions.

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Abstract: A metal member includes a plate-shaped portion provided on an upper main surface of a substrate, and includes a front main surface and a back main surface arranged in a front-back direction when viewed in an up-down direction. A first electronic component is mounted on the upper main surface of the substrate and is disposed in front of the metal member. A second electronic component is mounted on the upper main surface of the substrate and is disposed behind the metal member. A sealing resin layer is provided on the upper main surface of the substrate and covers the metal member and the one or more electronic components. The plate-shaped portion is provided with one or more lower notches extending upward from the lower side. The metal member further includes a plurality of foot portions. All of the plurality of foot portions extend backward from the lower side.

Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.

Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Abstract: Disclosed are a lead-free photodetector and a method for manufacturing the same. The lead-free photodetector includes a light-side electrode, a light-side conductive layer formed on the light-side electrode, a perovskite layer formed on the light-side conductive layer, a rear-side conductive layer formed on the perovskite layer, and a rear-side electrode formed on the rear-side conductive layer.

Abstract: An electronic device including an interposer is provided.

Abstract: This invention refers to a rheostatic braking method, applied on a BLDC motor (10) used in hermetic compressors, comprising: selecting a first phase and a second phase, connected to the BLDC motor (10), which will be short-circuited, at a certain electric position of the BLDC motor (10), wherein the first phase and the second phase selected are the phases having the major induced voltage and the minor induced voltage at a certain electric position of the BLDC motor (10); maintaining a third open phase to monitor the electric position of the BLDC motor (10) by means of monitoring the induced voltage at this third open phase; and separating the rheostatic braking in six electric positions, each electric position being associated to two electric sections: a first section before zero crossing of the induced voltage of the third open phase; and a second section after the zero crossing.

Abstract: A composition contains a naphthalocyanine derivative represented by the following formula: where R1 to R8 are independently an alkyl group and R9 to R12 are independently an aryl group, and at least one hydrogen atom in at least one selected from the group consisting of R9, R10, R11, and R12 is substituted by an electron-withdrawing group.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: A flexible polarizer and a flexible touch display device. The flexible polarizer includes: a support protective layer; a linear polarized layer provided on the side of the support protection layer and comprising an acidic substance; a retardation layer provided on the side of the linear polarized layer distant from the support protection layer, and bonded to the linear polarized layer by means of a first bonding layer; and a block layer provided on the side of the retardation layer distant from the linear polarized layer. The block layer is bonded to a flexible touch display panel of the flexible touch display device by means of the second bonding layer. The block layer is used for blocking the acidic substance in the linear polarized layer from permeating into the flexible touch display panel.

Abstract: An electrical power conversion control device of an electric automotive vehicle is obtained which is small in size and inexpensive with lower electric current consumption. In the power conversion control device, insulating power sources are each connected to gate drive circuits to form respective pairs therebetween; electric power whose voltage is regulated as a constant voltage by way of a constant-voltage circuit is supplied from a low-voltage battery to a low-voltage side of an insulating communications circuit, and a high-voltage side of the insulating communications circuit is operated by an insulating power source being at least one insulating power source among the insulating power sources; and a signal of a voltage of a high-voltage battery is insulated from the high-voltage side of the insulating communications circuit and transmitted therefrom to the low-voltage side thereof.

Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Abstract: A vehicle auxiliary power system includes a generator configured to be mechanically coupled to a power takeoff (PTO) of a vehicle via an offset gearbox. The generator produces AC power that is delivered to one or more power connection interfaces capable of industrial use. In some examples, the AC power may be converted to DC power for use by DC electronic systems or for charging one or more batteries. The vehicle auxiliary power system may include charge controllers, ECMs/ECUs, and other computing systems. As a result, a user may have an on-demand high-power electrical supply without the need of a second engine.

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: A coupler includes first and second electrodes and a nonlinear element including a Josephson junction. The first and second electrodes are spaced apart from a ground plane surrounding peripheries thereof and arranged opposed to each other. The first/second electrode includes two opposing portions extended toward first and second qubits/third and fourth qubits. At least either one of a gap between the first electrode and the ground plane facing the first electrode and a gap between the second electrode and the ground plane facing the second electrode, includes a gap width of at least a value of a same extent as or a fraction of a size of the first electrode or the second electrode.

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.