Abstract: A fast-in, slow-out sampling system that operates at a very high sampling frequency at high accuracy. The system includes a parallel processing sampling structure controlled by a precision pulse generation system.
Abstract: A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.
Abstract: Analog-to-digital conversion in which a coarse digital representation of an input analog signal is converted to a coarse analog representation, and the difference between the original analog signal and the coarse analog representation is determined. A ramp waveform signal is generated, and a change in that waveform by an amount substantially equal to the difference between the original analog signal and the coarse analog representation is sensed. A plural bit fine digital signal corresponding to the sensed change of the ramp waveform is produced. The combination of the coarse and fine digital signals constitute the digital representation of the input analog signal. In one embodiment, the ramp waveform is increased until it is equal to the difference between the analog signal and the coarse analog representation, whereupon the ramp waveform is digitized.
Abstract: An A/D converter includes a positive array of binary weighted capacitors with a common top plate (12) and a negative array of binary weighted capacitors with a common top plate (32). The positive and negative arrays are input to a differential amplifier (10) for measuring the differential voltage across the top plates. During the sample time, a differential input voltage is sampled on the bottom plates of the capacitors and the top plates of the capacitors are disposed at the common mode voltage of the input signal. This limits the input voltage across the capacitors to one-half the differential voltages of the input signal. During the hold mode and the redistribution mode, this presents a predetermined common mode input voltage to the amplifier (10) which is independent of the input signal.
Abstract: An analog-to-digital converter (ADC) controlled in a manner to increase its precision. The signal to be digitized is one input to an analog signal summing means whose output is the input to the ADC. A stepped or dither voltage signal is applied to the other summing means input during each analog signal sampling period of the ADC. The dither voltage steps are equal to the voltage equivalent of one ADC count plus 1/N where N is the number of steps per ADC count chosen to obtain a desired degree of precision in the digital signals that are output by the ADC. The dither voltage step that is combined with the current analog signal sample in the summing means amounts to displacing the sample in steps within each count of the ADC. The ADC converts each combined signal during a sampling interval to a succession of binary digital values which are summed.
Abstract: A recirculating type analog to digital converter is disclosed which has an auto-zero mode that is introduced prior to each conversion cycle. The loop is based on an arrangement of operational amplifiers and FET switches, and further includes a comparator circuit, a reference voltage source and a microprocessor which are coupled to the loop. Also coupled to appropriate points in the loop are three time gated integrator circuits which generate analog signals which respectively compensate for offset voltages of operational amplifiers in the loop, the offset voltage of the comparator circuit which is coupled to this loop, and the gain of the loop. The compensating signals which are generated in the auto-zero mode are applied to the loop during the conversion cycle.
Abstract: The predictive coder of the present invention is an apparatus for converting data into variable-length codes and outputting them, in which a differential data item is calculated from an input information data item and a predictive data item, a subsequent predictive data item is calculated using the quantized differential data item obtained by quantizing the differential data item, and coding is performed in such a manner that quantized differential data item indicating a data value having the maximum frequency of occurrence of quantized differential data items is coded as a code having a shortest length.
Abstract: An A/D converter comprises a resistor ladder connected between first and second reference potentials so that each connection tap provides a different divided reference potential. A plurality of first switches are each connected at their one end to one connection tap of the resistor ladder and at their other end to a corresponding number of common connection nodes. Also, a plurality of second switches are each connected at their one end commonly to an input for an analog voltage signal and at their other end to the corresponding common connection nodes. Each of the nodes is connected through one coupling capacitor to one amplifier having adapted to generate an output signal representative of whether the voltage of the input signal is higher or lower than a voltage appearing at the above mentioned one connection tap of the resistor ladder.
Abstract: An electricity metering transducer is disclosed which samples voltages and currents at an innerconnection terminal of an electrical energy distribution system, converts those samples to digital form and computes selected electricity metering quantities. In a multiphase system current and voltage signals are multiplexed to a pair of codecs, one for current signals and one for voltage signals. The period of the signals being sampled is detected and used to generate a substantially nonsynchronous sampling signal so that a sample migration system is created which provides a large number of samples of a composite wave form. The steps of a digitally generated stepwise approximation of a sawtooth waveform are summed with the sequential analog samples and then removed from the digital value of each sample by software operation in order to increase the resolution of the digital to analog conversion.
Abstract: A differential pulse code modulation system wherein digital code words assigned to the signal differences adjacent to the signal difference "Zero" have the same number of bits of one or the other logical level. In this manner, "d.c. voltage" information in the transmitted signal is neutralized.
Abstract: A high speed form of finite precision binary arithmetic coding comprises encoding/decoding performed in the logarithm domain, resulting in facilitated computation based on additions and subtractions rather than multiplications and divisions. In encoding and decoding, antilogs are used which are retrieved from an antilog table. The antilog table is characterized by the following constraints to assure decodability wherein for any two mantissas .alpha. and .beta. representing respective inputs to the antilog table:(a) antilog (.alpha.+.beta.).ltoreq.antilog (.alpha.) * antilog (.beta.); at least when (.alpha.+.beta.) is less than one; and(b) each antilog table output value is to be unique.
July 28, 1987
Date of Patent:
December 13, 1988
International Business Machines Corporation
Joan L. Mitchell, William B. Pennebaker, Gerald Goertzel
Abstract: A predictive time base control circuit for a waveform sampling system of the type which converts a sequence of analog waveform samples into a sequence of digital quantities for storage in an addressable acquisition memory. The time base circuit generates a sampling control signal which initiates sampling at the end of a time interval of programmable duration following detection of a triggering event in the waveform, and which maintains sampling thereafter at regular intervals. The time base circuit permits the sampling system to operate in an equivalent time mode in which repetitive waveform sections are sampled at progressively skewed sampling intervals with respect to a repetitive triggering event. The sampling control signal is also frequency divided, delayed, and then applied as a write control signal to the sampling system acquisition memory.
Abstract: A method for directly providing a conversion of an analog input signal to a digital signal in two's complement code with a sampled data converter. Positive and negative reference voltages and an analog ground voltage are required. After a sign bit determination of the input signal is made, the data converter is coupled between either a first pair of reference voltages or a second pair of reference voltages depending upon the sign bit. The first pair of reference voltages comprises the positive reference and ground reference, and the second pair of reference voltages comprises the ground reference and a negative reference. By selectively coupling the chosen reference voltages to the converter, a converter may directly output two's complement code.
November 28, 1986
Date of Patent:
December 13, 1988
Mathew A. Rybicki, James A. Miller, Ted A. Biggs, deceased
Abstract: A method and apparatus for high-resolution digitization of a signal with a large dynamic range employ an analog-to-digital converter having a bit number and having a measuring region which is smaller than the total range of measurement of the incoming signal, the range of measurement being divided into smaller measuring segments which partically overlap, each measuring segment having a size corresponding to the measuring ranges of the analog-to-digital converter. The information from the analog-to-digital converter controls a measurement segment selector such that the signal to be converted into digital form is within the selected segment. A new digital signal value is extrapolated at least from the two last bits from the analog-to-digital converter.
Abstract: An encoder device of the absolute position type for outputting a shift position or angle of rotation relative to the absolute position. The device comprises a code plate having first and second grid patterns wherein information is stored as 1 or 0 in a periodic manner at pitches slightly different from each other; first and second sensory arrays for detecting the first and second grid patterns; driving means for driving the sensors relative to the grid patterns and for obtaining an alternating signal from each array; and computation means for measuring the phase angle of the alternating signal from each array, and the phase angle difference therebetween and for calculating the position using such phase angles. Advantageously, the invention is suitable for miniaturization due to its simplicity, relaibility, and efficiency.
Abstract: Disclosed is a digital encoding apparatus related to CVSD techniques which provides an improved signal. The apparatus includes a comparator, comparing an analog input signal to a reconstructed analog signal and for generating the digital outputs in a manner similar to the CVSD technique. An integrating means, receives a slope control signal and the digital outputs to generate the reconstructed analog signal. The slope control signal, according to the present invention, is generated in a slope control means which includes means responsive to n digital outputs from serial clock cycles for generating an m-dimensional digital vector signal, and means responsive to the m-dimensional digital vector signal for generating the slope control signal. The m-dimensional digital vector signal is converted to an analog slope control signal by generating a scalar product of the m-dimensional digital vector signal with an m-dimensional weighting vector.
Abstract: A digital-to-analog converter circuit (10) comprises a current switch (22) that has differential input conductors (16a, 16b, . . . , 16n and 18a, 18b, . . . , 18n) which receive complementary logic voltage signals corresponding to a digital input word (X.sub.1, X.sub.2, . . . , X.sub.n). The current switch synthesizes an output signal (V.sub.o -V.sub.o) whose magnitude corresponds to the weighted value of the digital input word. The circuit further comprises a current reference source (60) that develops a reference current (I.sub.REF) from which transistor constant-current sources (48a, 48b, . . . , 48n) in the current switch derive binary-weighted currents to synthesize the output voltage signal. The current reference source includes an impedance element or resistor (70) through which the reference current flows and which is scaled to the load impedance connected to the current switch.
Abstract: Recovery from transmission errors is facilitated by initializing state variables to prescribed values in both a digital encoder used in transmitting a signal and a corresponding digital decoder used in receiving the signal when the transmission channel becomes inactive. Additionally, the values of the encoder and decoder state variables are held constant for up to a prescribed interval upon the transmission channel becoming inactive. The state variables are held constant until either the prescribed holding interval elapses or the transmission channel becomes active. If the prescribed holding interval elapses before the transmission channel becomes active the state variables are initialized to the prescribed values. However, if the encoder or decoder transmission channel becomes active before the prescribed holding interval has elapsed, the encoder or decoder, respectively, returns to its normal operative state and the state variables are allowed to adapt.
February 28, 1986
Date of Patent:
September 27, 1988
American Telephone and Telegraph Company, AT&T Bell Laboratories
Abstract: A converter of the flash type includes means for amplifying and d.c. level shifting portions of the input analog waveform fed to each A to D converter unit to provide each converter unit with a full voltage input swing relative to the reference voltage for conversion, thereby producing a more accurate digital output.
Abstract: An improved encoder alignment system is disclosed which provides an indication of the extent of misalignment and a measure of the rate at which the misalignment may be changing. The invention is adapted for use with a conventional encoder which provides a digital coarse word having at least significant bit and a digital fine word having a least significant bit and a most significant bit. The invention generates the exclusive or of the least significant bit of the coarse digital signal and the least significant bit of the fine digital signal to provide a first signal. The invention then generates the exclusive or of the first signal and the complement of the most significant bit of the fine digital signal to provide an output signal which represents the misalignment of the encoder.