Abstract: A weighted capacitor digital to analog converter is disclosed which requires only one stage and one conversion step. By the use of two reference voltages and two groups of capacitors in parallel, various capacitors in these groups can be selectively switched from the reference voltages to ground potential in response to input binary digit signals thereby presenting a predetermined amount of voltage to the output amplifier depending upon the number and particular combination of capacitors switched or non-switched to ground.

Abstract: A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively.

Abstract: The decoder herein described recovers the clocking and the data in a binary format from a three level coded signal. The decoder has application to data rates in excess of one half gigabits per second, which are common to optical communication channels. The decoder employs a comparator for evaluating to two bit accuracy each state of the signal, a two stage, two bit per stage shift register, and decision logic for recovering the data in a binary format. The decoder is monolithically integrated using buffered FET logic on a gallium arsenide substrate. In the decoder, the comparator is optimized by the use of three zero crossing detectors, one of which has a zero input for reference purposes, in combination with two internal voltage dividers and two external voltage references for achieving an accurate drift free determination of the levels of the three level code (TLC) signal.

Abstract: A charging circuit is provided to decrease the settling time of a reference capacitor storing a reference voltage for data acquisition circuits. The charging circuit includes one or more comparator circuits for comparing the voltage across the reference capacitor to the reference voltage provided by a reference source. If the voltage from the reference source deviates by a predetermined amount, one or more buffer circuits rapidly charge the reference capacitor to a voltage substantially equal to the new reference voltage. The reference source is then coupled directly to the capacitor to complete the charging of the capacitor to the new reference voltage.

Abstract: Conversion is achieved by subdividing the intergrate and deintegrate periods into a plurality of integrate and deintegrate phases. Power frequency rejection can be maintained by defining the combined integrate phases to integrate over at least one complete power line cycle. Sychronization of the integrate phases with the power line cycle is maintained by separating integrate phases with a combined deintegrate and rest phase of fixed duration.

Abstract: A sequence of digital data values is processed by deriving the average W.sub.n of two of the data values X.sub.n-1 and X.sub.n+1. If W.sub.n lies within the quantization step q centered on the data value X.sub.n, W.sub.n is adopted as a modified value of X.sub.n, but if W.sub.n lies outside the quantization step the modified value of X.sub.n is taken to be X.sub.n +q/2 or X.sub.n -q/2, depending on whether W.sub.n is greater or less than X.sub.n.

Abstract: By means of a controlled integrator, a noise component in the residual signal which is left after a conversion cycle of an analogue-to-digital converter can be eliminated for the major part. It is then possible to digitize this residual signal and thus to obtain additional bit information, as a result of which the range and the resolving power of the analogue-to-digital converter are increased.

Abstract: A shaft angle encoder comprises a code disc (21) mountable coaxially upon a rotary shaft (20) whose angular position is to be continuously measured. Coarse-bit angular position data are encoded digitally in Gray code by a pattern of opaque and transparent sectors provided on a plurality of inner annular tracks on the code disc (21). Fine-bit angular position data are encoded in analog triangular waveforms generated by the outermost annular track on the code disc (21). The analog position data are converted to fine-bit digital values, which are combined with coarse-bit digital values to obtain an angular position measurement. Alignment of the fine-bit digital values with the coarse-bit digital values obtained from the Gray code position data is accomplished by using information provided by overlapping the least significant bit of the coarse-bit digital values with the most significant bit of the fine-code digital values.

Abstract: A method and apparatus for transmitting and receiving messages by electromagnetic induction in a power restricted environment is disclosed in which the message bandwidth is narrowed prior to transmission and restored to its original breadth upon reception. This is accomplished by imputting a signal of a given duration into a signal storage means and outputting the signal from the storage means over a longer duration. The signal must be converted into a form suitable for storage. In a first preferred embodiment this is accomplished by converting the message to a digital form inputting it into a signal storage means, retrieving the message from storage at a rate different from the input rate and converting the retrived message to analog form. In a second preferred embodiment the signal is differentiated, and converted into a square wave; the zero crossings are identified and stored.

Abstract: A digital audio system for high-fidelity replication of wideband audio material. The system comprises a high-speed, low-noise and low-distortion, digital-to-analog converter including means for reducing spurious switching currents in the reconstructed audio signal. Such a converter is employed in both the encoding and decoding portions of the system.

Abstract: A digital-to-analogue converter includes a plurality of constant current sources and a calibration circuit for measuring the value or relative value of the current provided by one or more of the sources without interrupting operation of the digital-to-analogue converter. The calibration circuit carries out a routine whereby a number of measurements are obtained and averaged. Error signals in accordance with the averaged measurements are produced and used to correct for drift in the components of the current sources. Error correction may be achieved by adjusting the regulators themselves or by adding correction signals at other parts of the circuit.

Abstract: An improved signal converter which isolates a measurement voltage by converting an analog signal into a pulse-width-modulated output signal. The converter has a first integrator followed in series by a threshold value controller whose output signal actuates at least one reversing switch element which supplies to the summing point of the first integrator at which the signal prevails, and to the threshold value controller, either a positive or negative reference voltage. This signal converter has a very low offset and a high linearity at high sampling rates. The signal also has a second integrator whose summing point is also connected to the signal input and output of the reversing switch element. The output signal of the second integrator is the reference signal of the first integrator. The linearity of the signal converter is thus exclusively dependent upon the parameters of the second integrator.

Abstract: A signal conversion circuit is provided for obtaining quantized pattern data indicating a variation of photoelectric signal amplitudes along photosensor arrays by a variable pulse width signal indicating the amplitude of the photoelectric signal from each photosensor. A difference detector detects differences in pulse width of the variable pulse width signals to be compared to determine the extent of the variation with a predetermined unit precision. A comparison device determines whether or not the difference in pulse width exceeds a selected number of difference units and the pattern data indicating the variation are supplied only if the difference exceeds the selected number. Consequently, even if there are errors in the circuit elements constituting the signal conversion circuit, correct pattern data free from influence of such errors can be supplied.

Abstract: A programmable timer controls the duration of integration with respect to time of an unknown analog signal in accordance with a programmable time period established by a microprocessor. A switching logic successively transfers an analog signal and a voltage reference signal to an integrator under logic control actuated by the programmable timer. A comparator monitors the value of the integration of the reference voltage in order to control the time-out results of an event counter initiated simultaneously with input to the integrator of the reference voltage, for providing a digital count output signal to the microprocessor.

Abstract: An analog-to-digital converter comprising one or more charging and discharging circuits (C.sub.A and/or C.sub.B), a control circuit (6' and/or 6"), and a timer-counter (7). The control circuit performs the discharging operation alternately and continuously on the charging and discharging circuits. The timer-counter counts a predetermined number of times the discharging operation is performed so as to create a digital value (T).

Abstract: In a circuit arrangement for converting a digital input signal into an analog output signal, comprising a voltage divider chain which, between its ends which are supplied by at least one reference voltage, has a plurality of taps which, under the control of the digital input signal, are connectable to an output for deriving the analog output signal, a reduction in the output resistance and also an increase of the bandwidth of the analog output signal are accomplished because of the fact that any possible value of the digital input signal (B0 . . . B7) connects at least two taps (A0 . . . A257) of the voltage divider chain (W1 . . . W257) together to the output.

Abstract: A converter for converting a series of digital input bits to an analog output employs a direct current comparator having a magnetic core and primary and secondary ratio windings coupled with the core. The primary winding is divided into two sections. A first group of the more significant input bits varies the number of turns of the first primary section which is traversed by a first direct current. A second group of less significant input bits varies the number of turns of the second primary section traversed by a second direct current. A direct current is also passed through the secondary winding, this secondary current being varied proportionally with the number of turns of the first primary section traversed by the first primary current. Modulation-detection windings arranged inside the core (which also acts as a magnetic shield) detect any net ampere-turns unbalance of the primary and secondary currents in the ratio windings.

Abstract: A digital-analog converter wherein reference voltage is divided by a first string-like resistor array, whose two adjacent outputs are selected by a first switch array depending upon the contents of upper bits of a digital signal and applied to the both ends of a second string-like resistor array, and one of switches in a second switch array is selectively turned on responsive to the contents of lower bits of said digital signal to pick up one of the divided voltages of said second resistor array.

Abstract: A multiple function type D/A converter utilizing a ladder type resistance circuit, and capable of other mathematical functions in addition to the D/A conversion, having a series resistance circuit consisting of N number of resistors R2.sub.1 .about.R2.sub.n each having a resistance value R connected in series between an output terminal V.sub.o and one side of a terminal resistor R.sub.o which has a resistance value 2R and is connected on its other side to ground, such series circuit including a resistor connecting point between each adjacent pair of resistors R.sub.0, R2.sub.1 .about.R2.sub.N, and branching in parallel therefrom N+1 number of groups of parallel resistors 01.about.0n, 11.about.1n, . . . N1.about.

Abstract: A digital-to-analog converter system for converting a digital input signal having parallel words, each word including multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, is disclosed. The digital-to-analog converter system (10, 100, 200) includes pulse generating circuitry (11, 13, 111, 113, 211, 213) responsive to a first multi-bit group and a second multi-bit group of the digital input words for providing (a) a first pulse modulated signal as a function of the value of the first multi-bit group and (b) a second pulse modulated signal as a function of the value of the second multi-bit group; weighting elements (15, 19, 115, 119, 215, 219) for weighting the first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and output circuitry (20, 120, 220) for summing and filtering the weighted signals to provide an analog output signal that is representative of the digital input signal.