Abstract: A capacitive position encoder which provides a digital output indication of the relative position between two plates. One of the plates includes first and second conductive input areas which are separated by a gap having the shape corresponding to a square wave. The second plate includes a number of rectangular output pads whose length is equal to one-half of the wavelength of the square wave. The pads are separated from one another by an integral fraction of the wavelength. Periodic input signals which are the inverse of one another are applied to the input areas and are capacitively coupled to the output pads. When the degree of overlap between an output pad and the input areas is equal, a null signal will be generated. Each pad will provide a null signal corresponding to a different position of the plates.

Abstract: Absolute optical encoder device using a line array detector in conjunction with a single strip of encoding bars. The bars are orthogonal to the detector array line and may be long enough to allow motion parallel to the bars without loss of measurement continuity. High resolution is achieved by combining use of a small difference between the detector element spacing and the bar spacing in selected regions to produce a vernier effect, enabling measurement to the precision of a fraction of a detector element. High resolution is further achieved by traverse of a vernier regin edge across a multiplicity of detector elements upon which adjacent vernier regions are optically superimposed, and by identification of each vernier region as a unique member of a numbered series using distinguishable patterns in the space between vernier regions or in the structure of the vernier regions themselves.

Abstract: Each movable member (1) has a disk (6) which is mounted free to rotate about an axis (5) and which includes an annular area (7) of radial stripes (8) together with three concentric coding and read areas (9, 10, 11) having holes therethrough. The read station is equipped with a compressed air blast nozzle (15) for rotating each disk (6) presented thereto, together with a branch (17A) having suitable detectors (18, 19, 20) for detecting said holes and connected to electronic decoding circuits.

Abstract: An A/D converter has a transfer channel and a plurality of transfer electrodes for transferring a charge from the transfer channel in a predetermined direction. When the number of bits of the digital signal to be generated is n, the number of charge transfer stages is 2n. A ratio of the area of the last electrode of a given odd-numbered stage to that of the last electrode of the immediately preceding odd-numbered stage is 1:2. Each even-numbered transfer stage has a first transfer path for transferring a charge exceeding 1/2 of the channel potential of the last electrode of the immediately preceding stage and a second transfer path for transferring a charge which does not exceed 1/2 of the channel potential. The charge transferred to the first transfer path is detected. Transfer of the charge on the second transfer path to the next stage or sweeping thereof outside the charge transfer section is switched in accordance with the transfer charge detection signal.

Abstract: An analog/digital converter having a number of threshold circuits depending on the necessary bit resolution, the inputs of these threshold circuits being fed the analog signal to be digitized and the digitized signal being available at their outputs. The inputs of the threshold circuits are preceded by a modulator circuit in which the analog signal to be digitized is modulated by amplitude modulation upon a carrier frequency stable in frequency.

Abstract: A signal processor converts quadrature phase signals, from an encoder, representative of a measured parameter, into data which is directly readable by a computer and representative of the magnitude and direction of the current value of the parameter. The signal processor decodes binary signals representative of successive samples of the quadrature phase signals into UP signals, DOWN signals, ERROR signals and NO CHANGE signals. The UP and DOWN signals are converted into corresponding pulse streams which drive an up-down counter. Range control circuitry facilitates extension of the measuring range of the processor beyond that of the counter. Error control circuitry provides an ERROR INTERRUPT signal to the computer when an illegal condition occurs and also preserves the last valid data occurring before the illegal condition.

Abstract: Methods and apparatus for all-optical analog to digital conversion. An analog optical input signal is directed along a path comprising a series of level sensing means for determining whether its intensity is above or below a threshold value. The optical signals from successive level sensing means are directed in pairs to optical exclusive-or gates to provide a digital optical signal to at least one of a plurality of individual optical output means according to a designated digital coding system whereby the optical digital indication corresponds to the sensed level of intensity of the analog optical input signal. Apparatus comprising channel waveguides and integrated optical devices provide economical systems for high-speed computation and other uses.

Abstract: A data control circuit comprises a decoder adapted to generate weighted signals for determining the number of bits of data to be transferred; a detection circuit for detecting the output signals of the decoder to generate weighted signals corresponding to the transfer data bit number; and a propagation circuit responsive to the output signals of the detection circuit thereby to establish a propagation region where a predetermined signal propagates and a non-propagation region where the predetermined signal does not propagate and to generate from the non-propagation region the same number of activation signals as the bits of the data to be transferred.

Abstract: A D/A converter providing a binary weighted series of currents (I.sub.3, I.sub.4, I.sub.5) via first current-source transistors (T.sub.3, T.sub.4, T.sub.5) each in a given ratio to a reference current (I.sub.1) in a reference transistor (T.sub.1). The weighted currents are switched to analog output (15) or to positive supply terminal (20) via first switching devices (3.1, 3.2, 3.3). A control device includes a second current-source transistor (T.sub.8) connected to a reference-current source or to the positive supply terminal via a second switching device (4). The current (I.sub.8) in the transistor T.sub.8 has a given ratio to the reference current (I.sub.1). By connecting the second current-source transistor to the positive supply terminal or to the reference current source, the reference transistor carries the full reference current (I.sub.ref) from the reference current source or only a fraction of the full reference current, respectively. As the weighted currents are in a given ratio to the current (I.

Abstract: A multistage angle encoder includes a fine code disc which is connected via a reducing gear with at least one coarse code disc. In order unambiguously to allocate the coarse code information on the coarse code disc to the fine code information on the fine code disc, control information data is applied to the fine code disc to directly superimpose on the coarse code information of the coarse code disc. The control code information is provided in each case on two concentric control half-tracks of the fine code disc, and the coarse code information is provided in each case on two concentric coarse code half-tracks of the coarse code disc. The superposed coarse code half-tracks and control half-tracks are scanned in common by means of a single scanning field of the scanning plate.

Abstract: A digital-to-analog converter which develops an analog output representative of the difference between two digital inputs represented by the rates of two series of pulses. A prescribed number of pulses of each series is counted to develop two oppositely directed counter pulses, each having a duration dependent upon the time required to count the prescribed number of pulses. The counter pulses are integrated and the integration signal is sampled at the mid-point of each rise and decay. The average of the samples of each rise and decay represents the difference between the rates of the two series of input pulses.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: To eliminate crosstalk between successive measurements of an integrating analog-to-digital converter having MOS linear amplifiers (16) that as a result of ion distribution shift in its input devices gate oxide (24) tends to retain a conversion residue (R), at least one "dummy" conversion cycle (38) is executed prior to each input signal measurement. The "dummy" conversion cycle (38) reduces the residue (R) by moving input gate ions into stable positions corresponding to the magnitude of the input signal to be next measured.

Abstract: An output of a rotary or linear encoder of lower-precision (a subject encoder) is corrected according to that of higher-precision (a reference encoder) to provide higher precision output signals. In the present invention, a frequency multiplied pulse signal is obtained by multiplying a low precision output of a subject encoder by a multiplier. The number of pulses comprised in a portion of the multiplied pulse signal corresponding to a unit movement length of an object connected to the subject encoder is obtained by a hardware operation or by a program stored into a memory. A higher-precision output signal is obtained by dividing the frequency of the multiplied-frequency pulse signal of the subject encoder by a variable divisor corresponding uniquely to the number of high precision reference pulses between low precision subject encoder pulses when the object and the subject encoder are connected and moved.

Abstract: A D/A converter which converts a one-bit coded signal into an analog signal by means of an integrator comprising an operational amplifier (1) having an output (4) fed back to the inverting input (3) by means of a first capacitor (C.sub.1) and a resistor (R.sub.1). Depending on the value of the one-bit coded signal a positive current pulse or a negative current pulse is applied to the inverting input (3) of the integrator. The positive current pulses are generated by means of a switching network (10) comprising a second capacitor (C.sub.3) which is switched by means of a plurality of switches (S.sub.1 to S.sub.4). The negative current pulses are generated by means of a switching network (20) comprising a third capacitor (C.sub.4) which is switched by a plurality of further switches (S.sub.5 to S.sub.8). In order to ensure that the analog output signal is not distorted as a result of the positive and negative current pulses, a fourth capacitor (C.sub.2) is connected to the inverting input of the integrator.

Abstract: A digital-to-analog converter in accordance with the dynamic permutation principle in which a weighted series of accurate reference currents are generated by a cyclic permutation of currents which are equal to each other with a smaller degree of accuracy. The a.c. error component can then be eliminated by averaging the output signal of the converter over one full permutation cycle or an integral multiple thereof so that a signal without the error component is obtained by sampling at the end of every period. The setting of the digital-to-analog converter should not be changed during an averaging period.

Abstract: A television receiver includes a micro-computer which controls the receiver functions and provides on-screen display of messages for prompting the user. Display characters are compacted to minimize memory space by encoding the characters in 4-bit nibbles to maximize storage efficiency in a ROM organized to store 8-bit bytes.

Abstract: In a code converting device for converting first code data of scattered code form into second code data of consecutive data form, the first code data are divided at least into a first bit group and a second bit group, and the first bit group is supplied to a first memory to obtain first output data and second output data. The first output data and the second bit group are supplied to a second memory to obtain third output data. The second output data and the third output data are processed in a data processing unit to obtain the second code data.

Abstract: A system and method for generating a unique sync pattern that may be appended to a selected data sector of a disk storage system. The data to be stored in the disk storage system is encoded in accordance with a desired fixed rate run-length limited code, such as a 2,7 code. The unique sync pattern is generated by first encoding a prescribed data word in accordance with the desired code. At least one bit of the encoded prescribed data word is then changed in a manner such that the changed encoded word still complies with the coding rules of the desired code, yet the resulting bit pattern does not represent any valid sequence of data in accordance with the desired code. Hence, the changed encoded word may be readily distinguished from data, thereby providing the synchronization function, while still being handled and processed by the same encoding/decoding circuitry as is employed to handle and process the data.

Abstract: A digital-to-analog converter includes a plurality of constant current sources (401-407) arrayed in a prescribed order and connected with a grounding lead wire (70). The respective constant current sources (401-407) are selectively connected to a first bus (303) by corresponding switches (501-507), respectively. A decoder (2) outputs switching signals to the switches (501-507). The switching signals are outputted from the decoder (2) to the switches (501-507) so that the constant current sources symmetrically positioned with respect to the center of an array of the plurality of constant current sources (401-407) are sequentially connected to the first bus (303). Thus, the digital-to-analog converter is improved in linearity.