Abstract: The invention is a digital record/playback apparatus including an input digital filter, and A/D converter, a solid state memory, a D/A converter and an output digital filter. The entire system is driven off a single clock source which allows the frequent response of the filters to be modified simultaneous with the sampling frequency of the A/D and D/A converter. This allows the record/playback apparatus to record low frequency signals, such as medical data, as well as relatively high frequency signals such as voice, by simply changing the frequency of the clock source. In addition, the apparatus includes an expandable memory which allows recording of up to one hour or more of program material.

Abstract: An analog to digital converting device which can convert analog input signals individually into digital values of accurately corresponding magnitudes even when there is some difference in the input signals. The device comprises an integrating circuit which includes an operational amplifier for receiving an analog signal, an integrating capacitor connected between an input terminal and an output terminal of the operational amplifier, and a reset switch connected in parallel to the integrating capacitor. The integrating circuit is controlled to first perform an integrating operation and then an inverse integrating operation. A comparator is connected to an output terminal of the integrating circuit. A diode or transistor is connected in parallel to the integrating capacitor for limiting an amount of charge to be accumulated in the integrating capacitor by an inverse integrating operation to below a predetermined value.

Abstract: An analog-to-digital converter circuit includes a series of substantially identical stages, each receiving an incoming analog voltage. Reference terminals of the initial stage are biased to an initial reference voltage and ground, with subsequent first and second reference voltages determined in each preceding stage. A voltage divider consisting of a pair of matched resistors provides an output of one-half the reference voltage to a comparator. The comparator, having as its other input the incoming analog signal, generates a binary "one" or "zero" depending on whether the incoming signal is greater or less than the voltage divider output. The binary signal also controls switching circuitry which provides first and second reference signals to the next stage of the A/D converter. Responsive to a binary one from the converter, these reference signals are the reference voltage and one-half the reference voltage, respectively.

Abstract: Analog-to-digital converters are subject to errors including the known half least significant bit quantization error and also bit weighting errors due to lack of an ideal binary relationship between the transition points of all the bits. The known statistical average error reduction method in which a relatively small dither component is added to the analog input signal can only fractionally reduce overall error and has little effect on bit weighting errors. Herein the analog signal is added to a dither signal, for example a ramp signal, which varies through half the peak to peak digitization range of the converter so that irrespective of the input signal all output signal bits, other than the most significant bit, are "on" for one half of the sampling period. The result is that all the less significant bit errors are cancelled leaving only the easily compensated most significant bit error. A random component can be added to the dither signal to reduce the quantization error.

Abstract: An improved analog to digital converter suitable for fabrication on an integrated circuit and operable at high speed is disclosed.The converter is of the type when a voltage generated by a built-in D/A converter is successively subtracted from an input analog signal and the digital code of the built-in D/A converter is derived as the digital output when the coincidence between the voltage generated by the D/A converter and the input analog signal is detected by a comparator. The output of the comparator is fed back and superposed on the subtracted result as well as being used to control the D/A converter.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: An improved input ranging divider and method for an analog to digital converter in which a floating common input line to the A to D comparator is coupled through an R/2R resistive input ladder. A constant reference voltage is applied to the other comparator input. By applying an input voltage to a certain input terminal or terminals of the input ranging divider, while the remaining terminals are either grounded or left floating, a wide range of diverse operating ranges may be made available to an A to D converter while utilizing only a small overall number of inputs.

Abstract: A first data processing system sends a message to a second data processing system via a modem. A processor of the first data processing system executes the instructions of an encoding algorithm stored in a memory of the first data processing system thereby encoding the characters of the message as the message is sent from the first system to the second system. The processor, in conjunction with the encoding algorithm, encodes the characters of the message by locating unacceptable characters among the acceptable characters in the message, the unacceptable characters possessing more than one meaning and triggering the execution of a function other than the intended function. The acceptable characters do not possess any alternative meanings. A bias code is selected for the acceptable characters and a further bias code is selected for the unacceptable characters. The unacceptable characters are converted into modified acceptable characters.

Abstract: A subranging A/D converter generates high and low voltages using first and second DACs. A voltage divider receives the high and low voltages to generate plural reference voltages. A bank of comparators compares the analog voltage which is to be converted to each of the reference voltages, and a clocked logic circuit generates an intermediate digital signal indicative of the analog value relative to the plural reference voltages. The intermediate signal is used to decrement the high voltage and increment the low voltage, so that the reference voltages produced by the voltage divider assume subrange values. The process is repeated for as many clock cycles as is required to converge the high and low voltages to equal the analog voltage.

Abstract: A current rectifier is provided and generally comprises: a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I.sub.in ; and a first current mirror with its input connected to the drain of the n-channel transistor, and its output connected to the drain of the p-channel transistor. The current rectifier preferably also includes a second current mirror with the drain of the p-channel transistor as an input to the second current mirror and the rectified output current I.sub.out as an output of the second current mirror. If an offset to the rectified current is desired, a third current mirror having a bias or offset current as an input and the output of the second current mirror as an output may be included.

Abstract: A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

Abstract: A multichannel predictive gain amplifier system including a device for receiving input from a first channel and from a second channel, a variable gain amplifier, and a gain setting circuit for setting the gain of the variable gain amplifier. A switching device responsive to the input from the first and second channels sequentially connects each channel first to the gain setting circuit for determining the desired gain for that channel and then to the variable gain amplifier set to that desired gain.

Abstract: A decoder for the 2,7 variable length code. A four-bit shift register sliding block decoder detects the presence of the code's four-bit ending sequence and provides decoded binary output. The decoder has only a three-bit binary error propagation.

Abstract: Analog-to-digital conversion in which a coarse digital representation of an input analog signal is converted to a coarse analog representation, and the difference between the original analog signal and the coarse analog representation is determined. A ramp waveform signal is generated, and a change in that waveform by an amount substantially equal to the difference between the original analog signal and the coarse analog representation is sensed. A plural bit fine digital signal corresponding to the sensed change of the ramp waveform is produced. The combination of the coarse and fine digital signals constitute the digital representation of the input analog signal. In one embodiment, the ramp waveform is increased until it is equal to the difference between the analog signal and the coarse analog representation, whereupon the ramp waveform is digitized.

Abstract: A subranging analog-to-digital converter is disclosed. A coarse analog-to-digital converter has an analog input terminal coupled to a source of analog signal, a digital output terminal, and a range indication output terminal. First and second fine analog-to-digital converters each have an analog input terminal coupled to the analog signal source, a range selection input terminal coupled to the range indication output terminal, and a digital output terminal. A combining circuit has input terminals coupled to the digital output terminals of the coarse and first and second fine analog-to-digital converters. The coarse analog-to-digital converter operates on every clock cycle, and the fine analog-to-digital converters operate alternately on every other clock cycle to produce a sequence of digital samples representing the analog signal, one for each clock cycle.

Abstract: A combined digital-to-analog converter and latch memory circuit (10) includes an R-2R resistive ladder network (12) and a current-controlled latch memory 18. The R-2R resistive ladder network has plural input nodes (100 and 102) and an analog signal output (104). Each of the input nodes corresponds to a different bit of a digital word that is to be converted to an analog signal. The current-controlled latch memory includes plural subcircuits (14 and 16). Each of the latch subcircuits uses an amount of current to store the logic state of the bit of the digital word and to derive directly the node of the R-2R resistive ladder network. This configuration promotes the efficient use of space, power, and circuit elements.

Abstract: A method and apparatus for encoding binary data in which the method includes the steps of converting data words each containing N data bits to channel words each containing M data bits, and producing NRZI code data from the channel words. In the converting step, a data word is not converted in real time when the data word has a specific data bit pattern or when the data word is in a specific relationship to adjacent data words. This unconverted data word is converted to an established channel word which is so determined to reduce the DSV at a time when a predetermined number of data words which are convertible in real time have been inputted or when another data word which should be maintained unconverted has been inputted again. The established channel word is outputted after at least a delay time which is required to convert the unconverted data word to the established channel word.

Abstract: An optical rotary encoder is formed by a control pulse generator portion and a selector switch portion which are of the unitary construction. The control pulse generator portion is formed by a code plate having a plurality of alternately formed reflecting and non-reflecting areas, a plurality of light emitting and receiving elements facing the code plate and an inner shaft for rotating the code plate. The selector switch portion is formed by a second code plate having a plurality of light transmitting apertures, a plurality of light emitting elements facing the second code plate, a plurality of light receiving elements provided on the opposite side of the second code plate from those light emitting elements and an outer shaft for rotating the second code plate. The inner and outer shafts are connected to each other and have a common axis of rotation.

Abstract: A high level, staircase type of quasi-analog reconstruction of an analog input signal, such as an audio signal, initially involves a conventional derivation of a PCM signal from the analog input signal. The binary bits of each PCM codeword are considered as being C in number, of which an A number are major bits and a B number are minor bits. The A number of bits are converted to (2.sup.A -1) discrete decimal data bits, each of which controls the switching to and from a series voltage summation line of a discrete voltage V.sub.c, where ##EQU1## and V.sub.max is substantially the peak kilovolt amplitude to be provided in the reconstructed signal. Individual ones of the B bits directly control the individual switching to and from the summation line of discrete voltages of unequal magnitudes declining in one-half voltage increments from Vc/2 to Vc/2.sup.B.

Abstract: A digital-to-analog converter comprises a current source for supplying a current of predetermined magnitude to a circuit node, and a switch connected to the circuit node, and defining a first current path leading to a reference potential terminal and a second current path leading to an output terminal. The switch has an input terminal, at which it receives a first digital signal of one binary digit for conversion to analog form, and also has a reference terminal, and has a first condition, when the voltage at the reference terminal is higher than that at the input terminal, in which the current supplied to the circuit node is delivered to the output terminal, and a second condition, when the voltage at the reference terminal is lower than that at the input terminal, in which the current is delivered to the reference potential terminal.