Abstract: A substrate, a heat slug with an access cavity, a lid, and a heat sink having a stem are used to package a high applied power VLSI die. The substrate comprises a stepped housing cavity at its center, and a number of electrical contacts disposed at its underside. The inactive side of the high applied power VLSI die, the top surface and underside openings of the stepped housing cavity of the substrate, the heat slug including its access cavity, the stem of the heat sink, and the lid are coordinated in their sizes and geometric locations in view of the applied power and the heat transfer efficiency of the heat sink.

Abstract: A semiconductor device including a normally-on SI thyristor, and a MOSFET connected in cascade with the SI thyristor. The gate of the SI thyristor is connected to the source of the MOSFET. This arrangement makes it possible to turn the device on and off by controlling only the voltage gate of the MOSFET, obviating a current to maintain the on state of the device. The device needs little driving energy and has a low on state voltage and a high switching speed. It can readily be integrated into one chip.

Abstract: A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.

Abstract: Disclosed is a semiconductor device comprising a lead frame which includes a metal layer forming an outer lead, a thin metal layer forming an inner lead, an intermediate layer held between the thick metal layer and the thin metal layer for forming a connection portion between the outer lead and the inner lead and a bump positioned at the extreme end of the lead frame, whereby making the lead frame as an electrode leading means by directly connecting the bump to each electrode of a semiconductor element, wherein the lead formed of the thick metal layer has a thickness of 30 to 300 .mu.m, the lead formed of the thin metal layer has a thickness of 10 to 50 .mu.m, and the bump has thickness of 5 to 50 .mu.m.

Abstract: A standard lead frame has a carrier pierced to produce an opening sufficiently large to make room therein for the mounting of a semiconductor circuit chip. A heat sink for the semiconductor circuit chip is fastened into position in or just below the opening. The semiconductor circuit chip is then affixed directly to the heat sink. After wires have been bonded to connect contact areas of the chip to the conducting paths on the lead frame the unit is encapsulated in such a fashion that a major surface of the heat sink protrudes from the encapsulation. A standard lead frame may be used as the carrier.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over the integrated circuit. A nitrogen doped polysilicon layer is formed over the pad oxide layer. A thick nitride layer is then formed over the nitrogen doped polysilicon layer. An opening is formed in the nitride layer and the nitrogen doped polysilicon layer exposing a portion of the pad oxide layer. The nitrogen doped polysilicon layer is annealed encapsulating the polysilicon layer in silicon nitride. A field oxide region is then formed in the opening.

Abstract: A semiconductor structure according to the present invention includes a diffusion preventing layer for preventing a diffusion of a brazing metal layer, for instance, Au/In. The structure is interconnected to another structure by brazing.

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.

Abstract: A semiconductor device includes a semiconductor element attached to a support member by a junction material that includes a parent phase of a low-melting-point junction material and fine particles of a high-melting-point junction material which are uniformly dispersed in the low-melting-point material. By heating the junction material to a temperature higher than the melting point of the low-melting-point junction material and lower than the melting point of the high-melting-point junction material, the low-melting-point junction material is brought to a molten state, making the entire junction material fluid. Thus, the size of the junction material need not be adjusted to that of the semiconductor element. Further, with this semiconductor device, the contact area between the low-melting-point junction material and the high-melting-point junction material is extremely large so that the requisite time for making the composition of the junction material uniform is shortened.

Abstract: The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer.

Abstract: An axial lead frame including two side rails arranged opposite to each other and plural pairs of lead terminals separated from each other and located opposite to each other, in which a longer lead terminal and a shorter lead terminal of a pair of the lead terminals are alternately arranged to extend in parallel with each other in the equally spaced relationship between both side rails. And, a buffer member is formed at the substantially central part between both the side rails so as to allow the longer lead terminals extending from both the side rails toward the buffer member to be jointed to each other along the buffer member. A die pad is die-bonded to the foremost end of each of the longer lead terminal, while a pad is placed at the foremost end of each of the shorter lead terminal. Dam bars are bridged between adjacent lead terminals in order to prevent molten resin from flowing out during molding operation.

Abstract: A modified transistor layout allows operation at high frequencies without adversely effecting transistor power gain. The base and collector circuits are modified in order to minimize ground bar resistance and feedback problems between the input and output circuits. This reduces the applied negative feedback and maximizes gain. The collector contact bar and the output capacitor are mounted directly on the collector island such that the output capacitor is wired directly to the grounded package metal and the collector is wired to the collector contact bar. This eliminates the need to wirebond to areas on the collector island that are covered with the eutectic run-out which results from mounting the transistor chip on the collector island.

Abstract: A multiple-chip semiconductor device of the present invention comprises a first and a second leadframes. The same package envelops a power semiconductor chip mounted on a power chip mounting area in the first leadframe and a control chip mounted on a control chip mounting area in the second leadframe. In the device, the second leadframe is made of metal material which is processed easier than the first leadframe, and/or is finished thinner than the first leadframe. Thus, the multiple-chip semiconductor device can effectively dissipate the heat producing in the power semiconductor chip.

Abstract: A heat sink assembly adapted for use with an electronic device package such as a microprocessor having a grid array is shown having, in a first embodiment, a threaded base of a finned heat sink adapted to be received in a threaded bore of an adaptor which mounts onto the electronic device package. Desired thermal coupling is achieved by screwing down the heat sink in biasing engagement with the package. An alternate embodiment shows the heat sink which has a snap on flange to attach the heat sink to the adaptor.

Abstract: An alignment key (10) in a semiconductor substrate (40) is fabricated to display high optical contrast, and to prevent the diffusion of ionic contaminants through the alignment key (10) and into underlying portions of the semiconductor substrate (40). The alignment key (10) defines an enclosed structure formed by first and second metal layers (14, 20) which are electrically coupled by a filled via (22). A dielectric layer (42) is disposed between the metal layers (14, 20). A passivation layer (16) overlies an edge portion of the upper metal layer (14), however, the central portion of the upper metal layer (14) is bare. Slots (11, 12) in the upper metal layer (14) expose a portion of the lower layer (20) through the dielectric material (42). A high contrast scan signal (24) is generated as a continuous-wave laser beam traverses across the upper metal layer (14) and the slots (11,12).

Abstract: The present invention provides a multilayer ceramic package, which comprises a conductive layer, formed like a square layer, applying a power voltage V.sub.DD or a ground voltage V.sub.SS to a semiconductor device, and having a square hole in its central portion, a plurality of inner leads connected to the conductive layer at the inner portion of the conductive layer, and a plurality of outer leads connected to the conductive layer at the outer portion of the conductive layer, wherein if a first contact point between the inner lead and the conductive layer, a second contact point between the outer lead and conductive layer, a distance between adjacent two first contact points is C.sub.1, a distance between adjacent two second contact points is C.sub.2, a shortest distance from the first contact point to the second contact point is h, both C.sub.1 /h and C.sub.2 /h are 3/8 or less.

Abstract: A low inductance lead frame (10) is formed to have a die attach area (11). A plurality of intermediate connection bars (12,13,14,15) are positioned to be parallel to sides of the die attach area (11), and to be in a plane that is displaced perpendicularly from the die attach area (11). Each end of each intermediate connection bar is separated from an end of each other intermediate connection bar. Supports (17) extend from the die attach area (11) to the intermediate connection bars (12,13,14,15) to provide support for the intermediate connection bars 12,13,14,15). A plurality of leads (19,33,34) are positional in a plane and have a proximal end near the intermediate connection bars (12,13,14,15).

Abstract: An electrode assembly for a semiconductor device includes a contact layer formed on a semiconductor substrate and consisting mainly of a rare-earth metal or metals, or a silicide thereof, or a mixture thereof, and a diffusion barrier layer formed on the contact layer and consisting mainly of iron or an iron alloy. The assembly is bonded to a mount by a solder layer formed on the diffusion barrier layer and consisting mainly of lead and tin.

Abstract: A semiconductor assembly which includes a carrier and a semiconductor die is mounted on a printed wiring board. The die includes a top active surface and a bottom active surface. The two active surfaces are non-coplanar. The carrier is made from layers of a ceramic material. Holes are formed through all but one of the layers. The layers are laminated into an integral substrate, and the substrate is fired. The holes form a cavity into but not through the substrate. The number of layers, lamination pressures, and firing parameters are all adjusted in response to the thickness of the die to insure that the height of cavity walls approximately equals the thickness of the die. Continuous metallization is applied in the cavity and on a top surface of the substrate. The die is bonded in the cavity, and conductive bumps are formed on the die and the metallization.

Abstract: A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.