Abstract: There is provided a lead frame material formed of a Cu alloy for a resin sealed type semiconductor device, wherein the Cu alloy consists essentially of 2 to 4% Ni, more than 0.5 to 1%, Si, 0.1 to 2% Zn, more than 0.01 to 0.05%, Mg, 0.05 to 1% Sn, and the balance of Cu and inevitable impurities, the inevitable impurities containing 20 ppm or less sulfur (S) and 20 ppm or less carbon (C). The lead frame material formed of the Cu alloy has improved adhesion strength to an epoxy resin as a sealing material. A semiconductor device prepared from said lead frame material is also provided.

Abstract: There is disclosed a semiconductor device wherein a mounting substrate (3) including an insulating layer and a pattern electrode selectively provided on the insulating layer is mounted on a heat sink (6) having a major surface. A plurality of copper supports (2) each having a surface forming an angle of substantially not more than 90.degree. with the major surface of the heat sink (6) are provided on the mounting substrate (3) such that the respective surfaces are not opposed to each other, and each of the supports (2) supports a semiconductor body (1). The semiconductor bodies (1) are connected to the pattern electrode with wires (9), and a portion enclosing at least the wires (9) is filled with a silicone gel (11). This permits the semiconductor device of large capacity to be reduced in size and to have an improved durability.

Abstract: There is provided a packaged semiconductor device having a multi-layered lead frame assembly (38). An integrated circuit chip (12) has an active face (16) with a plurality of bond pads (18) disposed along its center line (14). A first pair of insulating adhesive tape strips (20) adhere a main lead frame (22) to the active face (16) of chip (12). A second pair of insulating adhesive tape strips (28) adhere a respective pair of bus lead frames (30) to the main lead frame (24). Welds (36) electrically interconnect selective leads (22) of main lead frame (22) with respective leads (32) of bus lead frames (30). Tab bonds (40) or wire bonds (42) electrically interconnect selective leads (24) of main lead frame (22) with bond pads (18) on chip (12).

Abstract: A plastic package type semiconductor device is composed of a rolled metal substrate made of copper or copper alloy and an insulating film formed on the surface of the substrate. The film may be a single-layer film made of silicon oxynitride or a composite film formed by laminating a silicon oxide layer and a silicon oxynitride layer (or a silicon nitride layer). A semiconductor element is mounted on the film or on the exposed surface of the substrate. Other passive elements are provided on the film. After connecting these elements with bonding wires, the entire device is sealed in a resin molding. This device is thus free of cracks due to difference in thermal expansion between the film and the substrate, or peeling due to moisture absorption.

Abstract: The disclosure relates to a semiconductor device comprising silicon having a substrate composed of low grade silicon, a silicon layer whose silicon purity is higher than that of the low grade silicon formed on the substrate and an electrode formed on the silicon layer. In the device, the low grade silicon may be selected from metallurgical grade silicon and silicon whose purity is less than 99.99%, and the silicon layer may be over 99.999% purity or semiconductor grade.

Abstract: A cooling device formed in a thermally conductive substrate having at least one microchannel of dimensions that induce capillary action and a surface in thermal contact with a heated region. The microchannel has a longitudinal opening oriented away from the heated region and is supplied with liquid coolant which is contained by a meniscus near the opening. The coolant vaporizes at the meniscus and absorbs heat but, due to increased pressure in the coolant contained by the meniscus, does not boil within the microchannel, allowing more liquid coolant contact with the thermally conductive substrate and walls. The vaporized coolant is discharged into a chamber facing the opening which can be at a lower pressure to remove additional heat by gaseous expansion. The discharge of gaseous coolant allows the capillary flow of the liquid coolant in the microchannels to be unimpeded, and may be augmented by a fluid pump.

Abstract: A leadframe for semiconductor devices is disclosed. The leadframe includes a die pad supported on the leadframe. A semiconductor chip is mounted on the die pad. The chip has a plurality of pads including at least one group of designated pads for communicating an identical signal, such as a power supply signal of the same level, with external circuits. A terminal on the leadframe is coupled to the group of designated pads. The terminal is attached to selected one or more leads on the leadframe for communicating the identical signal with the external circuits. The other pads on the chip, such as signal pads, are coupled to the corresponding leads on the leadframe. Thus, the total number of leads on the leadframe is reduced and more leads are available for the signal pads, resulting in efficient connections between the chip pads and the leads.

Abstract: A semiconductor apparatus is provided which includes a semiconductor chip on its one plane with a plurality of terminal electrodes, which are divided into a plurality of bundles, a bump provided on one of the bundles of terminal electrodes, a connect member of heat conductivity having a plane connected with the plane of the bump, and other connect members for connecting the other bundles of terminal electrodes regardless of the connect member. As a result, the terminal resistance of the semiconductor apparatus is considerably reduced.

Abstract: A synapse MOS transistor has gate electrodes of different lengths, different widths or different lengths and widths, between one source region and one drain region. Thus, when using the synapse MOS transistor to implement a neural network, the chip area can be greatly reduced.

Abstract: A semiconductor device capable of accommodating a larger semiconductor chip in its package than a comparable conventional device and providing flexibility in the design of the semiconductor chip. An insulating tape includes an opening which receives a plurality of electrode pads disposed on the central part of the top surface of the semiconductor chip. The insulating tape is disposed between the semiconductor chip and inner leads of a lead frame. Circuit pattern traces are present on top of the insulating tape. The inner end of each circuit pattern trace is connected to a corresponding electrode pad with a fine metallic wire, and the outer end of each circuit pattern trace is connected to the corresponding inner lead.

Abstract: An integrated circuit device having an array of flexible leads attached to the bottom of an integrated circuit package. There is provided a sheet of electrically conductive material. A plurality of slots are punched into the sheet, such that there is formed a plurality of beams. The beams are then bent into a spring shape. The sheet is placed over an integrated circuit package which has an array of contact pads extending across a bottom surface of the package. The beams are aligned and attached to the contact pads. The beams are then cut and separated from the remainder of the sheet. The sheet is removed, wherein there is constructed an integrated circuit package that has a two dimensional array of flexible leads.

Abstract: Encapsulation of semiconductor light emitting diodes, in particular laser diodes, characterized in that a gap is formed in an encapsulant, which is positioned in front of the light emitting facet of the diode, the gap preventing the encapsulant from adhering to the light emitting facet.

Abstract: A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

Abstract: A semiconductor device (10) includes a semiconductor die (18) and a heat spreader (16) adjacent the semiconductor die (18) for carrying heat away from the semiconductor die (18). The heat spreader (16) has a copper core (30) and a cupric oxide coating (32) formed on at least a portion of the core (30). A plastic package (12) is molded onto the semiconductor die (18) and the heat spreader (16) for supporting the semiconductor die (18) and the heat spreader (16). The cupric oxide coating (32) enhances adhesion of the heat spreader (16) to the plastic package (12).

Abstract: A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Abstract: A heat sink (44-48) is detachably mechanically connected to an electronic component package (10) by means of a pair of mutually spaced and parallel spring rods (16, 18) that are fixed to the electronic component package and span a recess (14) formed in a surface of the package. The heat sink is formed with a projecting latching member (50) having a short shank (52) on the end of which is formed a laterally outwardly extending flange (60). The flange has shoulders (62) that slope outwardly and away from the heat sink body and distal ends on which are formed cam surfaces (66) that slope inwardly away from the heat sink body. The latching member (50) of the heat sink is pressed into the electronic component package recess between the resilient rods (16, 18) to force the rods apart and to pass the outer most ends (64) of the flange this causes the rods to contact the flange shoulders (62) in a slightly outwardly bowed position of the rods.

Abstract: A semiconductor device including an insulating film substrate having a surface, a high frequency semiconductor chip disposed on the surface, and circuit elements disposed on the surface and connected to the semiconductor chip wherein the insulating film substrate is bent into a U-shape, laminated, and encapsulated with a resin. The package of the device is miniaturized.

Abstract: A light emitting semiconductor heterojunction includes a first layer of n-type semiconducting material comprising a Group II-VI material, and a second layer of p-type semiconducting diamond on the first layer. Preferably the Group II-VI material includes a Group II material selected from the group consisting of zinc and cadmium, and the Group VI material is selected from the group consisting of sulfur and selenium. The light emitting heterojunction will produce light having a wavelength in the range of about 440-550 nanometers, depending on the composition and the temperature of operation. One embodiment of the device is a surface emitting device and includes a contact layer on the diamond layer having a predetermined shape, such as a ring, overlying only a portion of the diamond layer for permitting surface emission of light from diamond layer.

Abstract: A molded plastic package for an integrated-circuit die includes a lead frame having inwardly extending tie bars and a central die-attach paddle. One side of the die-attach paddle has an integrated-circuit die fixed thereto. A heat sink member is resiliently fixed to the other side of the die-attach paddle using a layer of viscous thermal grease between the heat sink member and the other side of the die-attach paddle. At least one holes is formed through a portion of the lead frame and is engaged by a corresponding elongated stud on the heat sink. The elongated stud extends upwardly through the layer of thermal grease through the holes in the lead frame and terminates at the top of the molded plastic package. By extending to the top of the plastic package, the elongated stud firmly holds the heat sink against the bottom of the mold cavity during the encapsulation process. As a result, the bottom surface of the heat sink remains exposed after the encapsulation process.

Abstract: A semiconductor device package comprises a substrate (10), a flip-chip (16), an underfill adhesive (25), and a thermally and electrically conductive plastic material (20). A leadless circuit carrying substrate has a metallization pattern (13) on a first side (15), one portion of the metallization pattern being a circuit ground (17). The second side has an array of surface mount solder pads (24) electrically connected to the metallization pattern by means of at least one conductive via (26) through the substrate. A semiconductor device (16) is flip-chip mounted to the metallization pattern by means of metal bumps (22). An underfill adhesive (25) fills the gap between the semiconductor device and the substrate. A thermally and electrically conductive plastic material (20) containing metal particles is transfer molded to encapsulate the semiconductor device, the underfill adhesive, and a portion of the first side of the leadless circuit carrying substrate, forming a cover.