Abstract: Disclosed are an array substrate, display panel and display device. The array substrate includes: a substrate, where the substrate includes a display area and a peripheral circuit area surrounding the display area; the peripheral circuit area is provided with a gate drive circuit; the gate drive circuit includes a group of shift registers connected in cascade; a first metal layer; a second metal layer; scan lines and connection structures corresponding to the scan lines one-to-one; where the first metal layer includes the scan lines; the second metal layer includes the connection structures; the shift registers include scan signal output ends; the scan signal output ends are electrically connected to the scan lines one-to-one through the connection structures; at least one end of at least one scan line is provided with an electrostatic dispersion structure; the electrostatic dispersion structure includes an electrostatic dispersion line or an first electrostatic dispersion ring.

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Abstract: The present application provides an array substrate and a display panel. The array substrate includes a substrate, an active layer, a first metal layer, a second metal layer, a flexible material layer, and a source/drain layer which are disposed in a stack. The active layer forms a source and a drain and connected to a first connection member formed by the second metal layer through a first through-hole. The first connection member is connected to a doped region of the active layer by a second through-hole. An aperture of the first through-hole is greater than an aperture of the second through-hole. Therefore, a technical problem of a poor connection between the source/drain and the active layer is relieved.

Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Abstract: An array substrate, a manufacturing method thereof, a display panel and an electronic device are disclosed. The array substrate includes: a base substrate, a first electrode and a second electrode. The first electrode is disposed on the base substrate; the second electrode is disposed on the first electrode and is at least partly opposite to the first electrode in a direction perpendicular to the base substrate; the first electrode and the second electrode are electrically insulated from each other; a capacitor structure is constituted by a region of the first electrode and a region of the second electrode which are opposite to each other; and the capacitor structure includes a portion which forms at least part of a first recess.

Abstract: A display apparatus includes a substrate, a light-emitting device provided on the substrate, a driving transistor device configured to control the light-emitting device, a first power supply line electrically connected to a source region of the driving transistor device, a conductive pattern electrically connected to a gate electrode of the driving transistor device, and a second power supply line electrically connected to the first power supply line, wherein the conductive pattern and the first power supply line constitute a first capacitor, and the conductive pattern and the second power supply line constitute a second capacitor, wherein the first capacitor and the second capacitor are connected in parallel.

Abstract: An OLED display device including an OLED pixel driving circuit is provided. A driving thin film transistor in the OLED pixel driving circuit is configured as a double gate oxide thin film transistor, and a switch thin film transistor is configured as a top gate self-aligned oxide thin film transistor. A manufacturing method of a TFT array substrate is also provided, and the TFT array substrate is used for preparing the OLED display device.

Abstract: A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor.

Abstract: Disclosed is an array substrate, including a substrate, and a first data line, a first insulating layer and a second data line, which are disposed on the substrate in sequence. The first insulating layer is provided with a first via hole. The second data line is connected to the first data line through the first via hole. By configuring double-layer data lines, an area of the data lines is increased, thereby reducing the impedance of the data lines, thereby improving the charging capability of the remote pixels and the display quality of the panel.

Abstract: A substrate includes a base, a first insulating layer and a plurality of texture identifiers. The first insulating layer is disposed on the base and includes a plurality of via holes extending toward the base from a surface of the first insulating layer facing away from the base. The plurality of texture identifiers are disposed on the base. At least a part of each texture identifier is located within a respective one of the plurality of via holes. The texture identifier is configured to detect texture information.

Abstract: A display apparatus that includes a substrate, a first thin-film transistor and a second, thin-film transistor disposed on the substrate at different distances from a top surface of the substrate. A display device is electrically connected to the first thin-film transistor. The first thin-film transistor includes a first semiconductor layer in polycrystalline silicon and a first gate electrode that overlaps a channel region of the first semiconductor layer in a direction of a thickness of the substrate. The second thin-film transistor includes a second semiconductor layer including an oxide semiconductor. The first gate electrode has a stacked structure including a first layer and a second layer. The second layer includes titanium and the first layer includes a different material from the second layer.

Abstract: A method for manufacturing a light emitting device includes preparing a light transmissive member block including a first light transmissive member block having a plate like shape and including a resin containing at least one phosphor and a second light transmissive member block including a material harder than a material of the first light transmissive member block. Grooves are formed on an upper face of the second light transmissive member block. The light transmissive member block is divided at the grooves to obtain a plurality of light transmissive members each having a first light transmissive member and a second light transmissive member. A lower face of the first light transmissive member and an upper face of a light emitting element are bonded together such that a lower face perimeter of the first light transmissive member is located outside of an upper face perimeter of the light emitting element.

Abstract: The present disclosure provides a high electron mobility transistor (HEMT). The HEMT includes a substrate, a buffer layer, a channel layer, a barrier layer, a source, a drain, and a gate. The substrate, the buffer layer, the channel layer, the barrier layer, the source, the drain, and the gate are stacked in sequence in a thickness direction of the HEMT. The channel layer includes a doped semiconductor structure. The present disclosure further provides a method for manufacturing an HEMT. The HEMT has good performance and has features such as low drain electric field intensity, a high breakdown voltage, high stability, and low costs.

Abstract: A display device including a substrate including a first display region having a first width, a second display region having a second width smaller than the first width, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region, a first pixel in the first display region, a second pixel in the second display region, a first control line connected to the first pixel and extending in the first display region, a second control line connected to the second pixel and extending in the second display region, and a dummy line connected to the second control line in the dummy region, wherein the second control line is at a first conductive layer on a first insulating layer, the dummy line is at a second conductive layer on a second insulating layer on the first conductive layer.

Abstract: A change in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device including an oxide semiconductor. The semiconductor device including an oxide semiconductor film includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a third insulating film over the second insulating film. The second insulating film includes oxygen and silicon, the third insulating film includes nitrogen and silicon, and indium is included in a vicinity of an interface between the second insulating film and the third insulating film.

Abstract: A display panel includes a first transistor that contains oxide, a capacitor that includes a first electrode and a second electrode, a light emitting element connected to the capacitor and the first transistor, and an additional control electrode connected to the second electrode. The first and second electrodes are disposed on different layers from each other and are coupled to a first control electrode and a first output electrode, respectively, of the first transistor, and the light emitting element includes a light emitting layer. The additional control electrode overlap the first control electrode and the first semiconductor pattern, when viewed in a plan view. The additional control electrode and the second electrode are disposed on the same layer and form a single body.

Abstract: A driving substrate includes a base substrate. The base substrate has a display region and a peripheral region, and the peripheral region includes a bonding region between the display region and a first side face of the base substrate. The driving substrate further includes a plurality of first pads spaced apart from each other, which are disposed in the bonding region of the base substrate. A first side face of each first pad is flush with the first side face of the base substrate. A thickness of the first pad is approximately in a range from 0.5 microns to 2 microns.

Abstract: A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.