Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.

Abstract: A light emitting device includes a light emitting part 21, a black layer 51, and a light diffusion part 41 that is formed on or above the black layer 51. The black layer 51 is provided with an opening part 53 that allows light emitted from the light emitting part to pass through it. Then, light having passed through the opening part 53 passes through the light diffusion part 41.

Abstract: A flexible display apparatus includes a flexible display panel including a flexible substrate, a display area of the flexible substrate including a thin film transistor, an organic light emitting layer and a sensor electrode, and a peripheral area of the flexible substrate including a first alignment mark in which respective portions of two metal layers are stacked; a window on a first surface of the flexible display panel; and a protective film on a second surface of the flexible display panel. The first alignment mark is aligned with a reference point of the window and with a reference point of the protective film.

Abstract: A method for producing an image sensor comprises: depositing a first back-end-of-line, BEOL, layer above a substrate comprising an array of light-detecting elements, said BEOL layer comprising metal wirings being arranged to form connections to components on the substrate and together with depositing the first BEOL layer, improving planarization of the first BEOL layer by depositing a planarizing metal dummy pattern in the first BEOL layer, wherein a part of the planarizing metal dummy pattern is arranged above a light-detecting element, wherein the planarizing metal dummy patterns is formed from the same material as the metal wirings and is deposited to planarize density of the metal deposited in the first BEOL layer across a surface of the layer and wherein a shape and/or position of the metal dummy pattern above the array of light-detecting elements is designed to provide a desired effect on incident light.

Abstract: A light emitting element has first and second electrodes. In plan view, the first electrode has a first connecting portion, a first extending portion, and two second extending portions. The second electrode has a second connecting portion, and two third extending portions. The first extending portion extends linearly toward the second connecting portion, and the second extending portions are arranged on two sides of the first extending portion. The second extending portions each has two bent portions and a linear portion extending parallel to the first extending portion and disposed between the two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the second extending portions. The second extending portions extend beyond the second connecting portion. The first and second connecting portions are symmetrically arranged with respect to a virtual line parallel to one side of the light emitting element.

Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.

Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.

Abstract: An array substrate includes a pixel circuit and a light-emitting diode. The pixel circuit includes a driving transistor including a first active medium made of polysilicon, and a switching transistor including a second active medium made of polysilicon. The first active medium has a first grain size. The second active medium has a second grain size larger than the first grain size. The light-emitting diode is coupled to the pixel circuit.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: A display apparatus includes a substrate, a display unit, a pad portion, and a connection wire. The display unit is on the substrate. The display unit includes a pixel circuit and a display device electrically connected to the pixel circuit. The pad portion is at one side of a peripheral area outside the display unit. The pad portion includes a first conductive layer, a second conductive layer arranged on and electrically connected to the first conductive layer, and a third conductive layer arranged on and electrically connected to the second conductive layer. The connection wire connects the pad portion and the display unit to each other to transmit a signal input to the pad portion to the display device. The connection wire includes a same material as that of the first conductive layer.

Abstract: A display panel includes a substrate, a first metal layer arranged on the substrate, a first insulating layer disposed on the first metal layer, a second metal layer disposed on the first insulating layer, and a pixel unit. The first metal layer includes a first metal line and a second metal line. The first metal layer is spaced apart along a first direction. The second metal line is spaced apart along a second direction. The first metal line and the second metal line are connected at an intersection. The second metal layer includes a peripheral metal line. The peripheral metal line is electrically connected to the first metal line and the second metal line. The first metal line and the second metal line are connected to the pixel unit. The first metal line and the second metal line supply the pixel unit with a signal voltage.

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.

Abstract: Disclosed in various examples of the present invention are a display device and an electronic device having the same, the display device comprising: a display element; and a guide unit arranged on the display element, wherein the guide unit guides a propagation pathway of the light emitted from the display element. The display device and the electronic device having the same can provide a comfortable viewing environment by using the guide unit so as to guide the propagation pathway of the light emitted from the display element. The display device and the electronic device having the same can be variously implemented according to the examples.

Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.

Abstract: A method for fabricating a semiconductor device includes forming a channel region in a semiconductor substrate. The channel region is made of a first material. The method also includes forming source and drain regions in the semiconductor substrate. The method further includes forming a recess between the channel region and the drain region. The method further includes forming a tunnel barrier layer in the recess. The tunnel barrier layer is made of a second material, and a bandgap of the second material is greater than a bandgap of the first material. The method further includes forming a gate stack on the channel region.

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

Abstract: A multi-spectral photodetector is provided, comprising: a plurality of N photodetectors where N is an integer such that N?2, each photodetector comprising an anode and a cathode separated from one another by a region of interest, all produced in a semiconductor material; at least one electrical contact for all of the N anodes; and an electrical contact associated with each of the N cathodes; said photodetectors being stacked on top of one another such that the anodes and the cathodes and finally the regions of interest of two consecutive photodetectors in the stack are arranged face to face, this stack making it possible to define a face, termed the active face of the multi-spectral photodetector, common to all the photodetectors of the stack, defined by the face of the first region of interest of the first photodetector of the stack via which photons are intended to enter the stack.

Abstract: An electronic device including a base structure, a first pattern having at least one projection disposed on the base structure, a first conductive layer including a first portion disposed on the base structure and a second portion disposed on the first pattern and connected to the first portion, an insulating layer disposed on the first conductive layer covering the first portion and exposing the second portion, and a second conductive layer provided on the insulating layer and overlapping the first conductive layer. The second conductive layer is spaced apart from the first portion and is in contact with the second portion. Methods of manufacturing an electronic device capable of reducing the number of process steps in the manufacturing process are also disclosed.