Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract: A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction.

Abstract: A backplane structure containing a capacitor includes a substrate, a first conductive film disposes on the substrate, a second conductive member having one portion spaced apart from the first conductive film and another portion connected to the first conductive film, a third conductive film spaced apart from the first conductive film and the second conductive member, a fourth conductive member connected to the third conductive film, and a fifth conductive member having one portion connected to the fourth conductive member and another portion spaced apart from the second conductive member. The third conductive film is disposed between the first conductive film and the second conductive member in an insulation manner, and the second conductive member is disposed between the third conductive film, the fourth conductive member, and the fifth conductive member in an insulation manner.

Abstract: A display device includes: a substrate; a plurality of pixels provided in a pixel region of the substrate; a scan line and a data line, connected to each of the plurality of pixels; a first transistor connected to the scan line and the data line and a second transistor connected to the first transistor; a light emitting element connected to the transistor; a first blocking layer disposed between the substrate and the first transistor, the first blocking layer being electrically connected to the first transistor; and a second blocking layer disposed between the substrate and the second transistor, the second blocking layer being electrically connected to the second transistor, wherein the first blocking layer is connected to a gate electrode of the first transistor, and the second blocking layer is connected to any one of source and drain electrodes of the second transistor.

Abstract: An array substrate includes a base substrate, a thin film transistor on the base substrate, including a gate electrode connected to a gate line, an active layer, a gate insulating layer insulating the gate electrode from the active layer, a first electrode connected to a data line, and a second electrode spaced apart from the first electrode, and a micro light emitting diode on the base substrate, including a first electrode, a first buffer layer, a light emitting layer, and a second electrode, which are stacked on top of each other. The first buffer layer is in a same layer as the active layer. The second electrode of the thin film transistor is connected to one of the first electrode of the micro light emitting diode or the second electrode of the micro light emitting diode.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A transparent display panel includes a base and a plurality of sub-pixels disposed on the base. Each sub-pixel includes a light-emitting unit, and a light transmission portion disposed on at least one side of the light-emitting unit. The light-emitting unit includes at least one Micro-LED and a control circuit connected to the Micro-LED. The control circuit is configured to drive the at least one Micro-LED to emit light. The light transmission portion includes at least one of a transparent insulating portion or an opening.

Abstract: A display panel and a manufacturing method thereof and a display device using the same are provided. The display panel includes a display region and a non-display region. The display panel includes a substrate, a plurality of thin film transistors (TFTs) and a planarization layer sequentially stacked and at least one buffer unit disposed between the planarization layer and the substrate, wherein the buffer unit is located outside the TFT. The buffer unit is positioned in the display region and used for buffering stress of the display panel during bending.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: The present disclosure provides an organic light-emitting display panel, a method for making the same, and a display device including the same. The organic light-emitting display panel comprises an active region and a pixel spacer located within the active region, and the pixel spacer is provided with a buffer chamber.

Abstract: The present invention provides an array substrate and a display panel. A second data line is disposed on the array substrate, so that a first data line is connected to the second data line. Therefore, after the first data line is disconnected, signals can be transmitted from the second data line, which solves a technical problem that current display panels cannot solve poor display caused by disconnection of the data lines.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes a plurality of pixels, and the pixels include a main-pixel region and a sub-pixel region. The main-pixel region includes a common electrode portion including a sharing electrode, and a voltage of the sharing electrode is a fixed value. The sub-pixel region comprises a sub-driving thin film transistor and a sharing thin film transistor, wherein a drain of the sharing thin film transistor is connected to the sharing electrode, and a source of the sharing thin film transistor is connected to a drain of the sub-driving thin film transistor.

Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.

Abstract: There is provided a semiconductor device including an insulating substrate provided with a circuit surface, and an external terminal bonded to the circuit surface. The circuit surface has an upper surface that is in contact with and bonded to a part of a lower surface of the external terminal. In at least a part of a portion where the upper surface of the circuit surface and the lower surface of the external terminal are in contact with each other, a melted portion of the circuit surface and the external terminal is formed. A gap between the upper surface of the circuit surface and the lower surface of the external terminal has a size of 20 ?m or less. The circuit surface and the external terminal are each made of copper or copper alloy.

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions.

Abstract: A fabricating method of an array substrate includes: forming a first semiconductor pattern and a first insulating layer on a substrate; forming a first gate pattern and a second gate pattern isolated from each other; forming a second insulating layer; forming a second semiconductor pattern; forming a first metal pattern and a second metal pattern and a third metal pattern respectively lap-jointed with the second semiconductor pattern; forming a third insulating layer; and forming a first via hole, a second via hole, first source and drain electrodes, and second source and drain electrodes, where the first source and drain electrode are respectively connected to the first semiconductor pattern through the first via hole, and the second source and drain electrodes are respectively connected to the second semiconductor pattern through the second via hole.

Abstract: Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.

Abstract: A display panel includes a first display substrate including first to third pixel areas and a light blocking area that is adjacent to the first to third pixel areas and a second display substrate including first to third display elements respectively overlapping the first to third pixel areas. The first display substrate includes a base substrate, a first color filter overlapping the first pixel area and having a first color, a second color filter overlapping the second pixel area and having a second color different from the first color, a third color filter disposed on the base substrate, having a third color different from the first and second colors, and including a filter portion overlapping the third pixel area and a light blocking portion overlapping the light blocking area, and a light blocking member disposed on the light blocking portion and containing a black organic pigment.

Abstract: A method of manufacturing a display panel is that when the preparation of a front side of the display panel is finished, a structure composed of a protective layer, a sacrificial layer, a planarization layer, and a passivation layer is introduced as a protective film. The protective film structure does not contaminate vacuum equipment such as CVD or PVD. Moreover, the protective film structure has characteristics of hardness and abrasion resistance, so it does not produce residual stripper on the conveyor and does not interfere with the manufacturing process for the back side of the display panel. Moreover, the flatness of a surface of the film layer formed by CVD and coating machine is conducive to transfer and adsorption. The protective film may be completely removed by the means of LLO and dry-etching. The method of the process can effectively realize the double-sided process for single glass.