Patents Examined by Tan V. Mai
  • Patent number: 11227030
    Abstract: Techniques for data manipulation using a matrix multiplication engine using pipelining are disclosed. A first and a second matrix are obtained for matrix multiplication. A first matrix multiply-accumulate (MAC) unit is configured, where a first matrix element and a second matrix element are presented to the MAC unit on a first cycle. A second MAC unit is configured in pipelined fashion, where the first element of the first matrix and a second element of the second matrix are presented to the second MAC unit on a second cycle, and where a second element of the first matrix and the first element of the second matrix are presented to the first MAC unit on the second cycle. Additional MAC units are further configured within the processor in pipelined fashion. Multiply-accumulate operations are executed in pipelined fashion on each of n MAC units over additional k sets of m cycles.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 18, 2022
    Assignee: Wave Computing, Inc.
    Inventor: David John Simpson
  • Patent number: 11226792
    Abstract: A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 18, 2022
    Assignees: LAPIS SEMICONDUCTOR CO., LTD., TAMAGAWA SEIKI CO., LTD.
    Inventors: Masato Yamazaki, Hirofumi Maruyama
  • Patent number: 11216533
    Abstract: A grouping means 11 that extracts basis vectors from a set of basis vectors for a lattice having a predetermined relationship with a matrix used to generate a public key, and that groups the basis vectors such that a predetermined condition is satisfied. A sampling means 12 that samples, for at least one group, the same number of arbitrary values as the number of a plurality of basis vectors included in that group, in parallel for the individual basis vectors, onto a lattice constituted by the plurality of basis vectors, the arbitrary values serving as random numbers following a discrete Gaussian distribution. The predetermined condition is that each of the basis vectors included in a group is orthogonal to the other basis vectors included in the same group and is also orthogonal to Gram-Schmidt basis vectors, which are vectors obtained by orthogonalizing the other basis vectors by Gram-Schmidt orthogonalization.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 4, 2022
    Assignee: NEC CORPORATION
    Inventors: Yuki Tanaka, Kazuhiko Minematsu
  • Patent number: 11210063
    Abstract: A programmable device may be configured to support machine learning training operations using matrix multiplication circuitry implemented on a systolic array. The systolic array includes an array of processing elements, each of which includes hybrid floating-point dot-product circuitry. The hybrid dot-product circuitry has a hard data path that uses digital signal processing (DSP) blocks operating in floating-point mode and a hard/soft data path that uses DSP blocks operating in fixed-point mode operated in conjunction with general purpose soft logic. The hard/soft data path includes 2-element dot-product circuits that feed an adder tree. Results from the hard data path are combined with the adder tree using format conversion and normalization circuitry. Inputs to the hybrid dot-product circuitry may be in the BFLOAT16 format. The hard data path may be in the single precision format. The hard/soft data path uses a custom format that is similar to but different than BFLOAT16.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Bogdan Pasca, Sergey Gribok, Gregg William Baeckler, Andrei Hagiescu
  • Patent number: 11210066
    Abstract: A method for multiplying two binary numbers includes configuring, in an integrated circuit, a plurality of lookup tables based on a known binary number (w). The lookup tables can be configured in three layers. The method further includes receiving, by the integrated circuit, an input binary number (d). The method further includes determining, by the integrated circuit, a multiplication result (p) of the known binary number w and the input binary number d by determining each bit (pi) from p using the lookup tables based on specific combinations of bits from the known binary number w and from the input binary number d, wherein a notation jx represents the xth bit of j from the right, with bit j0 being the rightmost bit of j.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nimrod Megiddo, Charles Edwin Cox
  • Patent number: 11204978
    Abstract: A computing device includes a processor and memory storing instructions that are executable to determine a median of a first mixture distribution. The instructions are also executable to determine a parent mean, a parent standard deviation, and boundaries for each of multiple segments in the first mixture distribution. The instructions are also executable to determine a segment mean and a segment second moment for each segment based on the parent mean, the parent standard deviation, and the boundaries for the respective segment. The instructions are also executable to determine a scaled probability for each segment. The instructions are also executable to determine a mixture mean and a mixture standard deviation for the first mixture distribution based on the segment mean, the segment second moment, and the scaled probability for each segment in the first mixture distribution.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 21, 2021
    Assignee: CommScope Technologies LLC
    Inventors: Khalid W. Al-Mufti, Suryanarayana A. Kalenahalli, Navin Srinivasan, Ariful Hannan
  • Patent number: 11205115
    Abstract: Some embodiments provide a neural network inference circuit (NNIC) for implementing a neural network that includes multiple computation nodes at multiple layers. Each of a set of the computation nodes includes a dot product of input values and weight values. The NNIC includes multiple dot product core circuits for computing multiple partial dot products and a set of channel circuits connecting the core circuits. The set of channel circuits includes (i) a dot product bus for aggregating the partial dot products to compute dot products for computation nodes of the neural network, (ii) one or more post-processing circuits for performing additional computation operations on the dot products to compute outputs for the computation nodes, and (iii) an output bus for providing the computed outputs of the computation nodes to the core circuits for the core circuits to use as inputs for subsequent computation nodes.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 21, 2021
    Assignee: PERCEIVE CORPORATION
    Inventors: Kenneth Duong, Jung Ko, Steven L. Teig
  • Patent number: 11205134
    Abstract: Methods, systems, and apparatus for numerical quantum experimentation.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: December 21, 2021
    Assignee: Google LLC
    Inventor: Vasil S. Denchev
  • Patent number: 11204976
    Abstract: A method comprises receiving a kernel used to convolve with an input tensor. For a first dimension of the kernel, a square block of values for each single dimensional vector of the kernel that includes all rotations of that single dimensional vector is generated. For each additional dimension of the kernel, group blocks of an immediately preceding dimension into sets of blocks, each set of blocks including blocks of the immediately preceding dimension that are aligned along a vector that is parallel to the axis of the dimension; and generate, for the additional dimension, one or more blocks of values, each block including all rotations of blocks within each of the sets of blocks of the immediately preceding dimension. The block of values corresponding to the last dimension in the additional dimensions of the kernel is output as the expanded kernel.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 21, 2021
    Assignee: Groq, Inc.
    Inventors: Jonathan Alexander Ross, Tom Hawkins, Gregory Michael Thorson, Matt Boyd
  • Patent number: 11204739
    Abstract: A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 21, 2021
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mark Wallis, Yannick Sebillet
  • Patent number: 11200055
    Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Dan Baum, Zeev Sperber, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, Mark J. Charney, Barukh Ziv, Alexander Heinecke, Milind Girkar, Simon Rubanovich
  • Patent number: 11188115
    Abstract: A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.
    Type: Grant
    Filed: February 11, 2018
    Date of Patent: November 30, 2021
    Assignee: University of Science and Technology of China
    Inventors: Xi Qin, Wenzhe Zhang, Lin Wang, Yu Tong, Xing Rong, Jiangfeng Du
  • Patent number: 11188328
    Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A number of rank updates of a result matrix to store in an accumulator register having a predetermined size are determined, where the number of rank updates is based on the first precision and the first shape of the first input matrix, the second precision and the second shape of the second input matrix, and the predetermined size of the accumulator register. A plurality of linear algebra operations is repeated in parallel within the compute array to update the result matrix in the accumulator register based on the first input matrix, the second input matrix, and the number of rank updates.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jose E. Moreira, Brett Olsson, Brian W. Thompto, Silvia Melitta Mueller, Andreas Wagner
  • Patent number: 11188842
    Abstract: Examples are disclosed relating to obtaining a solution to a multiproduct formula of order m to solve a quantum computing problem comprising a product formula. One example provides a method comprising selecting a set of exponents kj, wherein each kj is a real number and is an exponent in a linear combination of product formulas. Based on the set of exponents kj, a set of pre-factors aj is determined based on an underdetermined solution to an m×M system of linear equations, where M is a number of lower-order product formulas in the linear combination of product formulas. The set of exponents kj and the set of pre-factors aj are used to solve the quantum computing problem comprising the product formula. By minimizing the set of exponents kj and the set of pre-factors aj, sparse solutions to the multiproduct formula are generated, reducing computational time and scaling.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: November 30, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vadym Kliuchnikov, Guang Hao Low, Nathan Wiebe
  • Patent number: 11188303
    Abstract: A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: November 30, 2021
    Assignee: Facebook, Inc.
    Inventors: Krishnakumar Narayanan Nair, Anup Ramesh Kadkol, Ehsan Khish Ardestani Zadeh, Olivia Wu, Yuchen Hao, Thomas Mark Ulrich, Rakesh Komuravelli
  • Patent number: 11182458
    Abstract: Embodiments of the present invention are directed to a new instruction set extension and a method for providing 3D lane predication for matrix operations. In a non-limiting embodiment of the invention, a first input matrix having m rows and k columns and a second input matrix having k rows and n columns are received by a compute array of a processor. A three-dimensional predicate mask having an M-bit row mask, an N-bit column mask, and a K-bit rank mask is generated. A result matrix of up to m rows, up to n columns, and up to k rank updates is determined based on the first input matrix, the second input matrix, and the predicate mask.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brett Olsson, Brian W. Thompto, Jose E. Moreira, Silvia Melitta Mueller, Andreas Wagner
  • Patent number: 11182668
    Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising a plurality of convolution engines each configured to perform convolution operations by applying filters to data windows, each filter comprising a set of weights for combination with respective data values of a data window; and one or more weight buffers accessible to each of the plurality of convolution engines over an interconnect, each weight buffer being configured to provide weights of one or more filters to any of the plurality of convolution engines; wherein each of the convolution engines comprises control logic configured to request weights of a filter from the weight buffers using an identifier of that filter.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 23, 2021
    Assignee: Imagination Technologies Limited
    Inventor: Christopher Martin
  • Patent number: 11163532
    Abstract: A method may include obtaining a set of multivariate quadratic polynomials associated with a multivariate quadratic problem and generating an Ising Model connection weight matrix “W” and an Ising Model bias vector “b” based on the multivariate quadratic polynomials. The method may also include providing the matrix “W” and the vector “b” to an annealing system configured to solve problems written according to the Ising Model and obtaining an output from the annealing system that represents a set of integers. The method may also include using the set of integers as a solution to the multivariate quadratic problem.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 2, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hart Montgomery, Arnab Roy, Ryuichi Ohori, Toshiya Shimizu, Takeshi Shimoyama, Jumpei Yamaguchi
  • Patent number: 11157594
    Abstract: A first group of modulo result matrices corresponding to modulo of elements of a first matrix by each of a plurality of moduli is stored. A second group of modulo result matrices corresponding to modulo of elements of a second matrix by each of the plurality of moduli is stored. It is determined whether an element operation of a multiplication of the first matrix with the second matrix can be performed using a first hardware multiplication module rather than a second hardware multiplication module. In response to a determination that the element operation can be performed using the first hardware multiplication module, the element operation is performed using the first hardware multiplication module including by multiplying one or more corresponding elements from the first group of modulo result matrices with one or more corresponding elements from the second group of modulo result matrices.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 26, 2021
    Assignee: Facebook, Inc.
    Inventor: Thomas Mark Ulrich
  • Patent number: 11157826
    Abstract: The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: October 26, 2021
    Assignees: UNIVERSITY OF MARYLAND, COLLEGE PARK, IONQ, INC.
    Inventors: Caroline Figgatt, Aaron Ostrander, Norbert M. Linke, Kevin A. Landsman, Daiwei Zhu, Dmitri Maslov, Christopher Monroe