Patents Examined by Tan V. Mai
  • Patent number: 10296868
    Abstract: A method is provided for providing a location of a product by converting a product code index to a location code value, comprising performing a step selected from the group consisting of: applying a function nP2vP to a product code index nP to provide a product code value vP and applying a mapping P2L to the product code value vP to provide a location code value vL; and applying a mapping P2L to a product code index nP to provide a location code index nL and applying a function nL2vL to the location code index nL to provide a location code value vL.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 21, 2019
    Inventor: Harold T. Fogg
  • Patent number: 10289602
    Abstract: A calculation apparatus in which a controlling unit performs a first storing process for storing a first value in a storing unit; a first displaying process for executing operation on a second value, using the first value to obtain and display a first and second output value on a displaying unit; a second displaying process for executing operation on a third value, using the first value to obtain and display a third and fourth output value on the displaying unit; a second storing process for adding the third output value to the first output value and the fourth output value to the second output value to obtain and store a first sum and a second sum in the storing unit; and a sum displaying process for displaying the first and second sum stored in the storing unit on the displaying unit in response to operation of the key unit.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 14, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Hironori Yoshikawa, Kazuhiko Arikawa, Toshibumi Takashima, Hiroaki Yoshizawa, Shinichi Tamamoto
  • Patent number: 10274989
    Abstract: Optical systems for performing matrix-matrix multiplication in real time utilizing spatially coherent input light and wavelength multiplexing.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Fathom Computing
    Inventors: William Andregg, Michael Andregg, Robert T. Weverka, Lionel Clermont
  • Patent number: 10275220
    Abstract: An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Sota Sakashita
  • Patent number: 10277202
    Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Sthanunathan Ramakrishnan, Pooja Sundar, Sashidharan Venkatraman
  • Patent number: 10261975
    Abstract: Provided are a four-dimensional non-equilibrium hyperchaotic system and analog circuit, based on the five simplest three-dimensional chaotic systems; an operational amplifier (U1), an operational amplifier (U2), and resistor and capacitor are used to constitute an inverting adder and an inverting integrator; multipliers (U3) and (U4) are used to perform multiplication operations; an 8V DC power supply is used for constant input; the operational amplifier (U1) and operational amplifier (U2) use LF347N, and the multipliers (U3) and (U4) use AD633JN; the operational amplifier (U1) is connected to the operational amplifier (U2) and the multiplier (U3); the operational amplifier (U2) is connected to the multiplier (U4), the DC power supply, and the operational amplifier (U1); the multiplier (U3) is connected to the operational amplifier (U1); the multiplier (U4) is connected to the operational amplifier (U2); the DC power supply is connected to the operational amplifier (U2); on the basis of the five simplest thre
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 16, 2019
    Assignees: Binzhou University
    Inventor: Zhonglin Wang
  • Patent number: 10249356
    Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 2, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Ning Ge, John Paul Strachan, Jianhua Yang, Miao Hu
  • Patent number: 10241756
    Abstract: A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
  • Patent number: 10241969
    Abstract: A data processing system that calculates a correlation coefficient between multiple variables includes a storage unit in which a table in which multiple correlation coefficients are stored is stored, a first selection unit that makes a selection to determine whether or not calculation of a first correlation coefficient that is a correlation coefficient between a first variable and a second variable is indispensable, a second selection unit that selects a third variable which is a variable that results from storing in the table a second correlation coefficient that is a correlation coefficient representing a relationship with the first variable, and a third correlation coefficient that is a correlation coefficient representing a relationship with the second variable, and a first determination unit that determines whether or not the calculation of the first correlation coefficient is indispensable, based on the second correlation coefficient and the third correlation coefficient.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 26, 2019
    Assignee: HITACHI, LTD.
    Inventor: Tomoaki Akitomi
  • Patent number: 10237676
    Abstract: This application describes methods of signal processing and spatial audio synthesis. One such method includes accepting an auditory signal and generating an impression of auditory virtual reality by processing the auditory signal to impute a spatial characteristic on it via convolution with a plurality of head-related impulse responses. The processing is performed in a series of steps, the steps including: performing a first convolution of an auditory signal with a characteristic-independent, mixed-sign filter and performing a second convolution of the result of first convolution with a characteristic-dependent, sparse, non-negative filter. In some described methods, the first convolution can be pre-computed and the second convolution can be performed in real-time, thereby resulting in a reduction of computational complexity in said methods of signal processing and spatial audio synthesis.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 19, 2019
    Assignee: University of Maryland, College Park
    Inventors: Yuancheng Luo, Ramani Duraiswami, Dmitry N. Zotkin
  • Patent number: 10235341
    Abstract: Method for solving the decomposition-coordination calculation based on Block Bordered Diagonal Form (BBDF) model by using data center. During the solving process, partitioning the electric power system network by using the existing network partitioning method to achieve the grid partition, and setting the parameters of virtual memories firstly, thus to establish the bin-packing model with the priority of energy efficiency; and then, setting each calculating step of the decomposition-coordination calculation based on BBDF as a task. Through the manners that servers host VMs and VMs map tasks, the decomposition-coordination algorithm can be executed in data center, and the running time and energy consumption of data center can be calculated. The calculating time of decomposition-coordination algorithm is shortened and the energy consumption in data center.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 19, 2019
    Assignee: Tianjin University
    Inventors: Ting Yang, Wenping Xiang, Yingmin Feng, Haibo Pen, Mingyu Xu, Jinkuo You, Hongtao Wang
  • Patent number: 10235135
    Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Klaus M. Kroener, Cedric Lichtenau, Silvia M. Mueller, Andreas Wagner
  • Patent number: 10228910
    Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Petra Leber, Cedric Lichtenau, Silvia M. Mueller
  • Patent number: 10229092
    Abstract: Systems and methods which provide robust low-rank matrix approximation using low-rank matrix factorization in the lp-norm space, where p<2 (e.g., 1?p<2), providing a lp-PCA technique are described. For example, embodiments are configured to provide robust low-rank matrix approximation using low-rank matrix factorization in the least absolute deviation (l1-norm) space providing a l1-PCA technique. Embodiments minimize the lp-norm of the residual matrix in the subspace factorization of an observed data matrix, such as to minimize the l1-norm of the residual matrix where p=1. The alternating direction method of multipliers (ADMM) is applied according to embodiments to solve the subspace decomposition of the low-rank matrix factorization with respect to the observed data matrix. Iterations of the ADMM may comprise solving a l2-subspace decomposition and calculating the proximity operator of the l1-norm.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 12, 2019
    Assignee: City University of Hong Kong
    Inventors: Wen-Jun Zeng, Hing Cheung So, Jiayi Chen
  • Patent number: 10223073
    Abstract: Apparatuses and methods of manufacturing same, systems, and methods for performing recursive operations using a partial remainder-divisor (PD) table are described. In one aspect, it is determined whether a current cell in the PD table indicated by a current partial remainder/radicand row value and a current divisor/root column value is outside a primary region of the PD table. If the current cell is outside the primary region of the PD table, at least one of the current partial remainder/radicand row value and the current divisor/root column value are adjusted so that the indicated current cell falls within the primary region of the PD table.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Bonnie Collett Sexton, James T. Longino
  • Patent number: 10216483
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: T. J. O'Dwyer, Pierre Laurent
  • Patent number: 10216702
    Abstract: A machine generates and provides a digital impact matrix including a first matrix and, in some embodiments, a second matrix, the first matrix including a plurality of impacts that various digital technologies have on various organizational processes. In some embodiments, the first matrix includes a plurality of magnitudes of impacts, while the second matrix includes a plurality of business values of impact that the various digital technologies have on the various organizational processes. A user interface is provided to assign impact categorizations to the impacts and of the first matrix and the second matrix, if applicable, and to display a graphical representation of the digital impact matrix.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Accenture Global Solutions Limited
    Inventors: Silke Lehmann, Ankur Saxena
  • Patent number: 10216703
    Abstract: A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 26, 2019
    Assignee: Spero Devices, Inc.
    Inventors: Jai Gupta, Nihar Athreyas, Abbie Mathew, Blair Perot
  • Patent number: 10216482
    Abstract: The speed of pen position detection is improved without increasing the circuit area and the current consumption. A sampling circuit samples a signal and outputs sampling data. A arithmetic circuit calculates a real part and an imaginary part of the sampling data. The arithmetic circuit classifies the real part of the sampling data into one of a plurality of groups and classifies the imaginary part of the sampling data into one of the groups according to an order of output of the sampling data from the sampling circuit. Then, the arithmetic circuit adds together real parts of sampling data belonging to a group and adds together imaginary parts of sampling data belonging to a group for each of the groups, and calculates amplitude and phase of the signal by using an addition result of the real parts and an addition result of the imaginary parts of each of the groups.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Masato Hirai, Yuki Higuchi, Takeshi Kuwano, Kosuke Fuwa
  • Patent number: 10216705
    Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 26, 2019
    Assignee: Google LLC
    Inventors: Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Olivier Temam, Jonathan Ross, Christopher Aaron Clark