Patents Examined by Tan V. Mai
  • Patent number: 10810281
    Abstract: An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arthur John Redfern, Donald Edward Steiss, Mihir Narendra Mody, Tarek Aziz Lahlou
  • Patent number: 10802800
    Abstract: Systems, apparatuses, methods, and computer program products are disclosed for quantum random number generation (QRNG). An example method includes generating, by a QRNG chip, a series of particles and transmitting the series of particles through a double-slit structure comprising a first slit and a second slit. The example method further includes detecting, by the QRNG chip, a first subseries of particles transmitted through the first slit to generate a first detected subseries of particles. The example method further includes detecting, by the QRNG chip, a second subseries of particles transmitted through the second slit to generate a second detected subseries of particles. The example method further includes decoding, by the QRNG chip, the first detected subseries of particles and the second detected subseries of particles to generate a decoded set of bits that, in some instances, may be used to generate a random number, a session key, or both.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: October 13, 2020
    Assignee: WELLS FARGO BANK, N.A.
    Inventor: Masoud Vakili
  • Patent number: 10803258
    Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 13, 2020
    Assignee: Lightmatter, Inc.
    Inventors: Tyler J. Kenney, Martin B. Z. Forsythe, Tomo Lazovich, Darius Bunandar
  • Patent number: 10803379
    Abstract: Provided are systems, methods, and integrated circuits for a neural network processing system. In various implementations, the system can include a first array of processing engines coupled to a first set of memory banks and a second array of processing engines coupled to a second set of memory banks. The first and second set of memory banks be storing all the weight values for a neural network, where the weight values are stored before any input data is received. Upon receiving input data, the system performs a task defined for the neural network. Performing the task can include computing an intermediate result using the first array of processing engines, copying the intermediate result to the second set of memory banks, and computing a final result using the second array of processing engines, where the final result corresponds to an outcome of performing the task.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 13, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Randy Huang, Ron Diamant
  • Patent number: 10803259
    Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 13, 2020
    Assignee: Lightmatter, Inc.
    Inventors: Tyler J. Kenney, Martin B. Z. Forsythe, Tomo Lazovich, Darius Bunandar
  • Patent number: 10803383
    Abstract: Provided is a neuromorphic arithmetic device. The neuromorphic arithmetic device may include a synapse circuit, a metal line having an inherent capacitance component, an oscillator, a comparator, and a capacitance calibrator. The synapse circuit may be configured to perform a multiplication operation on a PWM signal and a weight to generate a current. The metal line may include a metal line capacitor in which a charge of the current is stored. The oscillator generates a plurality of pulses on the basis of the charge stored in the metal line capacitor. The comparator may compare a frequency of the plurality of pulses and a target frequency, and may generate a control signal on the basis of a result of the comparison. The capacitance calibrator may adjust a capacitance value of the metal line capacitor on the basis of the control signal.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 13, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kwang Il Oh, Sung Eun Kim, Seong Mo Park, Hyung-Il Park, Joo Hyun Lee
  • Patent number: 10795967
    Abstract: A computer-implemented method, computer program product, and apparatus are provided. The method includes substituting N×N first integer elements, among a plurality of first integer elements obtained by dividing first integer data expressing a first integer in a first digit direction, into a first matrix having N rows and N columns. The method further includes substituting each of one or more second integer elements, among a plurality of second integer elements obtained by dividing second integer data expressing a second integer in a second digit direction, into at least one matrix element of a second matrix having N rows and N columns. The method also includes calculating a third matrix that is a product of the first matrix and the second matrix. The method includes outputting each matrix element of the third matrix as a partial product in a calculation of a product of the first integer and the second integer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jun Doi
  • Patent number: 10779771
    Abstract: A method and apparatus which combines multiple simultaneous signals thought to contain a common periodic component by performing principal component analysis on each of the multiple signals, finding the weight of the first principal component, and then adding the multiple signals together in a weighted sum according to the weight of the first principal component. The method and apparatus further includes a way of combining signals from successive overlapping time windows in real time by differentiating the signal and forming as each output signal sample the value of the preceding signal sample summed with the differential of the signal, weighted by weights based on the amplitude of the differential signal at that time point.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 22, 2020
    Assignee: OXEHEALTH LIMITED
    Inventor: Nicholas Dunkley Hutchinson
  • Patent number: 10783216
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 22, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Anthony Richard Huggett, Martin Stuart Abrahams
  • Patent number: 10776451
    Abstract: A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a controller configured to select a size for the FFT; and a multiplexer configured to: receive data output from one of the intermediate stages and data output from the final stage; select one of the received outputs in dependence on the selected FFT size; and output said selection as a result of the FFT on the input dataset.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 15, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Debashis Goswami
  • Patent number: 10776078
    Abstract: In one embodiment, in a first mode, first and second input operands having a first data type are multiplied using one or more of a plurality of multipliers, and in second mode, a plurality of input operands having a second data type are multiplied using the plurality of multipliers. Accordingly, multiplier circuitry may process different input data types and share circuitry across the different modes. In some embodiments, in the first mode, products may be converted to a third data type, and in the second mode, multiple products may be concatenated. Values in the third data type, in the first mode, and concatenated values having the second data type, in the second mode, may be added across different multimodal multipliers to form a multiply-accumulator. In some embodiments, the plurality of multiply-accumulators may be configured in series.
    Type: Grant
    Filed: September 23, 2018
    Date of Patent: September 15, 2020
    Assignee: Groq, Inc.
    Inventors: Christopher Aaron Clark, Jonathan Ross
  • Patent number: 10768894
    Abstract: A processor includes: a plurality of processor cores; and an internal memory configured to be accessed from the plurality of processor cores, wherein an arithmetic circuit provided in any of the plurality of processor cores includes: a plurality of first registers provided in a first stage of the arithmetic circuit, a regular addition circuit including a first adder and a second register, the first adder being configured to add a plurality of outputs of the plurality of first registers, the second register being configured to be provided in a second stage and latch an output of the first adder, an overtaking addition circuit including a second adder, the second adder being configured to add a plurality of outputs of the plurality of first registers, and a synthesis circuit including a third adder and a third register.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Katsuhiro Yoda, Mitsuru Tomono, Takahiro Notsu, Makiko Ito
  • Patent number: 10761808
    Abstract: Systems, apparatuses, methods, and computer program products are disclosed for quantum random number generation (QRNG). An example method includes generating, by a QRNG chip, a series of particles and transmitting the series of particles through a double-slit structure comprising a first slit and a second slit. The example method further includes detecting, by the QRNG chip, a first subseries of particles transmitted through the first slit to generate a first detected subseries of particles. The example method further includes detecting, by the QRNG chip, a second subseries of particles transmitted through the second slit to generate a second detected subseries of particles. The example method further includes decoding, by the QRNG chip, the first detected subseries of particles and the second detected subseries of particles to generate a decoded set of bits that, in some instances, may be used to generate a random number, a session key, or both.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 1, 2020
    Assignee: WELLS FARGO BANK, N.A.
    Inventor: Masoud Vakili
  • Patent number: 10762162
    Abstract: An apparatus and method of low complexity optimization solver for path smoothing with constraint variation are herein disclosed. According to one embodiment, an apparatus includes an L1 central processing unit (CPU) configured to transform an L1 trend filtering problem to a primal-dual linear programming (LP) optimization problem pair; and an L1 arithmetic logic unit (ALU) connected to the L1 CPU and configured to solve a primal problem of the primal-dual LP optimization problem pair with an extended full tableau simplex method.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Binnan Zhuang, Dongwoon Bai, Jungwon Lee
  • Patent number: 10762164
    Abstract: A computing device and related products are provided. The computing device is configured to perform machine learning calculations. The computing device includes an operation unit, a controller unit, and a storage unit. The storage unit includes a data input/output (I/O) unit, a register, and a cache. Technical solution provided by the present disclosure has advantages of fast calculation speed and energy saving.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 1, 2020
    Assignee: Cambricon Technologies Corporation Limited
    Inventors: Tianshi Chen, Xiao Zhang, Shaoli Liu, Yunji Chen
  • Patent number: 10754618
    Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
  • Patent number: 10747846
    Abstract: Matrix processing includes: initializing a current matrix based at least in part on an original matrix; iteratively determining a matrix property using a plurality of iteration cycles, including, in an iteration cycle: partitioning the current matrix to obtain a plurality of partitions, wherein the plurality of partitions includes a submatrix; modifying the submatrix based at least in part on other partitions of the plurality of partitions to provide a current matrix for a next iteration; and continuing to iterate until a condition is met. Matrix processing further includes obtaining the matrix property from an iteration result; and outputting the matrix property.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 18, 2020
    Assignee: Cyber Atomics, Inc.
    Inventor: Roy Batruni
  • Patent number: 10747502
    Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Xilinx, Inc.
    Inventors: Satyaprakash Pareek, Anup Hosangadi, Bing Tian, Ashish Sirasao, Yao Fu, Oscar Fernando C. Fernandez, Michael Wu, Christopher H. Dick
  • Patent number: 10747642
    Abstract: Systems and methods are described for efficiently detecting an optimal number of behaviors to model software system performance data and the aspects of the software systems that best separate the behaviors. The behaviors may be ranked according to how well fitting functions partition the performance data.
    Type: Grant
    Filed: October 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Oracle International Corporation
    Inventors: Sampanna Shahaji Salunke, Dustin Garvey, Uri Shaft, Brent Arthur Enck, Timothy Mark Frazier, Sumathi Gopalakrishnan, Eric L. Sutton
  • Patent number: 10742196
    Abstract: Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 11, 2020
    Assignee: NXP B.V.
    Inventor: Stefan Quitzk