Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract: An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

Abstract: A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

Abstract: Embodiments of quantum ring oscillator-based coherence preservation circuits including a cascaded set of stages are described. Embodiments of such quantum ring oscillator-based coherence preservation circuits allow the internal (superpositioned) quantum state information of stored qubits to be preserved over long periods of time and present options for the measurement and potential correction of both deterministic and non-deterministic errors without disturbing the quantum information stored in the structure itself.

Abstract: A system for evaluating a piecewise linear function includes a first look-up table with N entries, and a second look-up table with M entries, with M being less than N. Each of the N entries contains parameters that define a corresponding linear segment of the piecewise linear function. The system further includes a controller configured to store a subset of the N entries from the first look-up table in the second look-up table. The system further includes a classifier for receiving an input value and classifying the input value in one of a plurality of segments of a number line. A total number of the segments is equal to M, and the segments are non-overlapping and contiguous. The system further includes a multiplexor for selecting one of the M entries of the second look-up table based on the classification of the input value into one of the plurality of segments.

Abstract: A computing device selects a piecewise linear regression model for multivariable data. A hyperplane is fit to observation vectors using a linear multivariable regression. A baseline fit quality measure is computed for the fit hyperplane. For each independent variable, the observation vectors are sorted, contiguous segments to evaluate are defined, for each contiguous segment, a segment hyperplane is fit to the sorted observation vectors using a multivariable linear regression, path distances are computed between a first observation of the and a last observation of the sorted observation vectors based on a predefined number of segments, a shortest path associated with a smallest value of the computed path distances is selected, and a fit quality measure is computed for the selected shortest path. A best independent variable is selected from the independent variables based on having an extremum value for the computed fit quality measure.

Abstract: A method, apparatus, and computer program product for improved pseudo-random number generation are provided. An example method includes receiving, by a computing device, a request for a pseudo-random number, selecting, by extraction circuitry of the computing device, a first parameter from a server parameter dataset, and obtaining a first value for the first parameter. The method further includes selecting, by the extraction circuitry, a second parameter, and obtaining a second value for the second parameter. The method includes generating, by transformation circuitry, the pseudo-random number based on the first value and the second value.

Abstract: According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

Abstract: A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

Abstract: Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: An apparatus includes a first holding unit and a second holding unit configured to hold first-type data and second-type data, respectively, a first operation unit configured to execute a first product-sum operation based on the first-type data, a branch unit configured to output an operation result of the first product-sum operation in parallel, a sampling unit configured to sample the operation result and to output a sampling result, and a second operation unit configured to execute a second product-sum operation based on the second-type data and the sampling result.

Abstract: A processing device may analyze a set of time series data using a time series forecasting model comprising an attributes model and a trend detection model. The attributes model may comprise a modified gradient boosting decision tree (GBDT) based algorithm. Analyzing the set of time series data comprises determining a set of features of the set of time series data, the set of features including periodic components as well as arbitrary components. A trend of the set of time series data may be determined using the trend detection model and the set of features and the trend may be combined to generate a time series forecast.

Abstract: A resistive matrix computation circuit and methods for using the same are disclosed.

Abstract: A scalable matrix computation circuit and methods for using the same are disclosed. In one embodiment, a matrix computation circuit includes a plurality of first operand memory configured to store a first set of input operands of the matrix computation circuit, a plurality of second operand memory configured to store a second set of input operands of the matrix computation circuit, where the first and second sets of input operands are programmable by the controller, a plurality of multiplier circuits arranged in a plurality of rows and plurality of columns, where each row receives a corresponding operand from the first set of operands, and each column receives a corresponding operand from the second set of operands, and the each corresponding operand from the each row is used multiple times by the multiplier circuits in that row to perform multiplications controlled by the controller, and a plurality of aggregator circuits configured to store charges produced by the plurality of multiplier circuits.

Abstract: A feature transformation apparatus includes at least a combination storage part that stores a combination with respect to a set of features, wherein data is approximately represented as a sum of the combination of the features; and a transformation part that transforms at least the combination so as not to change the sum of the combination of the set of features.

Abstract: Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.

Abstract: The embodiments of this application provide a method and device for optimizing neural network. The method includes: binarizing and bit-packing input data of a convolution layer along a channel direction, and obtaining compressed input data; binarizing and bit-packing respectively each convolution kernel of the convolution layer along the channel direction, and obtaining each corresponding compressed convolution kernel; dividing the compressed input data sequentially in a convolutional computation order into blocks of the compressed input data with the same size of each compressed convolution kernel, wherein the data input to one time convolutional computation form a data block; and, taking a convolutional computation on each block of the compressed input data and each compressed convolution kernel sequentially, obtaining each convolutional result data, and obtaining multiple output data of the convolution layer according to each convolutional result data.

Abstract: A method of generating a random uniformly distributed Clifford unitary circuit (C) includes: generating a random Hadamard (H) gate; drawing a plurality of qubits from a probability distribution of qubits; applying the random H gate to the plurality of qubits drawn from the probability distribution; and generating randomly a first Hadamard-free Clifford circuit (F1) and a second Hadamard-free Clifford circuit (F2). The first and second Hadamard-free Clifford circuits is generated by at least randomly generating a uniformly distributed phase (P) gate, and randomly generating a uniformly distributed linear Boolean invertible conditional NOT (CNOT) gate, and combining the P and CNOT gates to form the first and second Hadamard-free Clifford circuits. The method further includes combining the generated first Hadamard-free circuit (F1) and the second Hadamard-free Clifford circuit (F2) with the generated random Hadamard (H) gate to form the random uniformly distributed Clifford unitary circuit (C).