Abstract: Provided are systems, methods, and integrated circuits for a neural network processing system. In various implementations, the system can include a first array of processing engines coupled to a first set of memory banks and a second array of processing engines coupled to a second set of memory banks. The first and second set of memory banks be storing all the weight values for a neural network, where the weight values are stored before any input data is received. Upon receiving input data, the system performs a task defined for the neural network. Performing the task can include computing an intermediate result using the first array of processing engines, copying the intermediate result to the second set of memory banks, and computing a final result using the second array of processing engines, where the final result corresponds to an outcome of performing the task.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: A computing device and related products are provided. The computing device is configured to perform machine learning calculations. The computing device includes an operation unit, a controller unit, and a storage unit. The storage unit includes a data input/output (I/O) unit, a register, and a cache. Technical solution provided by the present disclosure has advantages of fast calculation speed and energy saving.

Abstract: A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

Abstract: Techniques regarding an iterative energy-scaled variational quantum eigensolver process are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a read-out component that determines a ground state energy value of a quantum Hamiltonian by employing a variational quantum eigensolver (VQE) algorithm, wherein VQE algorithm utilizes a symmetry that emerges at an energy scale of the quantum Hamiltonian.

Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

Abstract: The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located.

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry are described. The acceleration circuitry may be deployed in a memory device and can include a memory resource and/or logic circuitry. The acceleration circuitry can perform operations on data to convert the data between one or more numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The acceleration circuitry can perform arithmetic and/or logical operations on the data after the data has been converted to a particular format. For instance, the memory resource can receive data comprising a bit string having a first format that provides a first level of precision. The logic circuitry can receive the data from the memory resource and convert the bit string to a second format that provides a second level of precision that is different from the first level of precision.

Abstract: The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.

Abstract: Disclosed are a method and apparatus for storing data. The method includes: acquiring data to be stored; converting the data to be stored from an initial data type to a target data type, a data length corresponding to the target data type being less than that corresponding to the initial data type; and storing the data to be stored of the target data type to a database. In the method according to the present disclosure, a storage space occupied by the data to be stored in the database is greatly reduced. In addition, the method according to the present disclosure is performed prior to lossy or lossless data compression storage of the data to be stored in the related art. That is, on the basis of a compression ratio when the data to be stored is stored in the related art, the present disclosure further improves a compression effect of the data to be stored by reducing the data length when the data to be stored is stored, and further saves storage resources of the database.

Abstract: A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a separation of the quantum circuit into local layers, and entangling layers; compiling the local layers; compiling the entangling layers, separate from the step of compiling the local layers, transforming the quantum gates of those entangling layers so that they contain only collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category; and a step of grouping together the compiled local layers and the compiled entangling layers into a compiled quantum circuit.

Abstract: According to an aspect of an embodiment, operations include receiving a Quadratic Integer Programming (QIP) problem including an objective function and a set of constraints on integer variables associated with the objective function. The operations further include obtaining an approximation of the QIP problem by relaxing the QIP problem and generating an approximate solution by solving the obtained approximation. The operations further include generating a Quadratic Unconstrained Binary Optimization (QUBO) formulation of the QIP problem based on the generated approximate solution and the received QIP problem. The operations further include submitting the generated QUBO formulation to an optimization solver machine and receiving a solution of the submitted QUBO formulation from the optimization solver machine. The operations further include publishing an integral solution of the received QIP problem on a user device based on the received solution.

Abstract: A system and methods for designing single-stage hardware sorting blocks, and further using the single-stage hardware sorting blocks to reduce the number of stages in multistage sorting processes, or to define multiway merge sorting networks.

Abstract: An arithmetic processing apparatus includes a memory and a processor. The processor coupled to memory and configured to determine an individual not to be evolved to an individual of a second generation from among a plurality of individuals in a first generation based on a predetermined reference for calculation completion of fitness calculation for each of the plurality of individuals, the second generation being a generation next to the first generation, and determine to cause the determined individual to evolve to an individual of a generation next or subsequent to the second generation.

Abstract: Methods, systems and apparatus for simulating quantum systems. In one aspect, a method includes the actions of obtaining a first Hamiltonian describing the quantum system, wherein the Hamiltonian is written in a plane wave basis comprising N plane wave basis vectors; applying a discrete Fourier transform to the first Hamiltonian to generate a second Hamiltonian written in a plane wave dual basis, wherein the second Hamiltonian comprises a number of terms that scales at most quadratically with N; and simulating the quantum system using the second Hamiltonian.

Abstract: A method is provided that includes performing, by a processor in response to a vector finite impulse response (VFIR) filter instruction, generating of a plurality of filter outputs using a plurality of coefficients and a plurality of sequential data elements, the plurality of coefficients specified by a coefficient operand of the VFIR filter instruction and the plurality of sequential data elements specified by a data operand of the VFIR filter instruction, and storing the filter outputs in a storage location specified by the VFIR filter instruction.

Abstract: Systems and methods are provided for channelizing. A first stage can provide a WOLA filter bank that can apply a single multiplier resource to perform window weighting for multiple WOLA filter banks. The first stage can remove mixer-based post FFT adjustment and provide equal functionality with a particular modification of tuning mixers at inputs of second stage FIR paths. The first stage can include a variable decimation, using a particular implementation of variable sample block size.

Abstract: A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.