Abstract: A classification system is provided for classifying text-based business summaries, referred to herein as “summaries,” against a hierarchical industry classification structure. The classification system includes a word-based sub classifier that uses a neural network to generate a vector space for each summary in a training set, where each summary in the training set is known to correspond to a particular industry classification in the hierarchical industry classification structure. Weight values in the hidden layer of a neural network used by the word-based sub classifier are changed to improve the predictive capabilities of the neural network in the business summary classification context. Embodiments include increasing representation in the training set for underrepresented parent industry classifications and attributes of the hierarchical industry classification structure, such as distances between industry classifications and whether industry classifications are in the same subgraph.

Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

Abstract: Techniques for data manipulation using integer matrix multiplication using pipelining are disclosed. A first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n are obtained for matrix multiplication within a processor. The first and second integer matrices employ a two's complement variable radix point data representation. The first and second integer matrices are distilled into (j×j) submatrices. A first variable radix point format and an initial value for an accumulator register are configured dynamically. A first variable radix point format is configured dynamically for the first integer matrix and a second variable radix point format is configured dynamically for the second integer matrix. Multiply-accumulate operations are executed in a pipelined fashion on the (j×j) submatrices of the first integer matrix and the second integer matrix, where a third variable radix point format is configured for the result.

Abstract: A system comprises a matrix processor unit that includes a first type of register, a group of a second type of registers, and a plurality of calculation units. The first type of register is configured to concurrently store values from different rows of a first matrix. At least a portion of the first type of register is logically divided into groups of elements, and each of the groups corresponds to a different row of the first matrix. Each of the second type of registers is configured to concurrently store values from a plurality of different rows of a second matrix. Each of the calculation units corresponds to one of the second type of registers and is configured to at least in part determine a corresponding element in a result matrix of convoluting the second matrix with the first matrix.

Abstract: A secure table reference system includes a first combining part 11n for generating [v?] of v? ? Fm+nt in which d and v are combined, a difference calculation part 12n for generating [r?] of r? that has a difference between a certain element of r and an element before the certain element as an element corresponding to the certain element, a second combining part 13n for generating [r?] of r? ? Fm+nt in which r? and an m-dimensional zero are combined, a permutation calculation part 14n for generating {{?}} of a permutation ? that stably sorts v? in ascending order, a permutation application part 15n for generating [s] of s: =?(r?) obtained by applying the permutation ? to r?, a vector generation part 16n for generating [s?] of a prefix-sum s? of s, an inverse permutation application part for generating [s?] of s? obtained by applying an inverse permutation ??1 of the permutation ? to s?, and an output part 17n for generating [x] of x ? Fm consisting of (nt+1)th and subsequent elements of s?.

Abstract: In accordance with an aspect of the present disclosure, there is provided a convolution operation method.

Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.

Abstract: Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the inverse of the lossy compression. The compression circuit and decompression circuit have parallel multiplier circuits and parallel adder circuits to perform the lossy compression and lossy decompression, respectively.

Abstract: In one aspect, A method for computing neural network computation includes the step of, providing plurality of neurons, coupled with a plurality of inputs, through a plurality of synapses. Each neuron output is given by an equation ?(Xi*Yi)+b. Xi*Yi comprises the ith synapse of the neuron. Xi comprises a set of Xi input vectors. Each Xi input vector is translated into an equivalent electrical signal for an ith corresponding synapse of the plurality of neurons, Yi comprises a set of Yi weight vectors, wherein each Yi weight vector comprises a parameter for the ith corresponding synapse of the plurality of neurons. Each synapse is a sub-system and the sub-system comprises a negative vector neural circuit, a positive vector neural circuit, and a set of four non-volatile memory weight cells for computation. The method includes the step of identifying the input vector x as a positive input vector or a negative input vector.

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

Abstract: Methods and apparatus for performing video processing matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for discrete cosine transform (DCT) matrix transformations and performing DCT matrix operations therein. Exemplary embodiments described herein perform DCT matrix-matrix multiplication operations within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one embodiment, matrix-matrix multiplication operations are obtained using separate matrix-vector products. In one exemplary embodiment, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage.

Abstract: A product-sum operation device includes a product operator, a sum operator, and a malfunction determiner. The product operator includes a plurality of product operation elements (10AA) to (10AC), and each of the plurality of product operation elements (10AA) to (10AC) is a resistance change element. The sum operator includes an output detector that detects the sum of outputs from the plurality of product operation elements (10AA) to (10AC). The malfunction determiner determines that a malfunction has occurred when the sum detected by the output detector exceeds a specified value. The specified value is a value equal to or greater than a maximum value of the sum that can be detected by the output detector when the plurality of product operation elements (10AA) to (10AC) all operate normally.

Abstract: A test and measurement instrument for generating an analog waveform, including an interpolator configured to receive a digital signal and output interpolated samples of the digital signal at a sample rate, a filter modulation controller configured to output first filter coefficients at a first time and second filter coefficients at a second time, a convolver configured to generate a convolved signal by convolving the interpolated samples of the digital signal and the first filter coefficients and convolving the interpolated samples of the digital signal and the second filter coefficients; and a digital-to-analog converter configured to convert the convolved signal to an analog signal based on a fixed, constant clock signal.

Abstract: An apparatus to facilitate matrix multiplication operations. The apparatus comprises multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations on a plurality of multiplicands and perform addition operations on results of the N×N multiplication operations.

Abstract: The illustrative embodiments provide a method, system, and computer program product. In an embodiment, a method includes receiving a set of Pauli observables. In an embodiment, a method includes initializing a measurement basis, the measurement basis comprising a set of Pauli bases equivalent to a number of qubits of a quantum processor. In an embodiment, a method includes creating a list of a set of Bell basis candidates, each of the set of Bell basis candidates configured to measure at least one of the set of Pauli observables. In an embodiment, a method includes selecting a Bell basis candidate from the set of Bell basis candidates. In an embodiment, a method includes reconfiguring the measurement basis to replace a subset of the set of Pauli bases with the selected Bell basis candidate.

Abstract: The present disclosure relates to a method for controlling execution of a GEMM operation on an accelerator comprising multiple computation units, a first memory device, and a second memory device. The method comprises determining an execution manner of the GEMM operation, the execution manner comprising partition information of the GEMM operation and computation unit allocation information of the partitioned GEMM operation; generating one or more instructions to compute the partitioned GEMM operation on one or more allocated computation units; and issuing the one or more instructions to at least one of a first queue and a second queue, which enables at least one of a first local controller and a second local controller to execute the one or more instructions, wherein the first local controller and the second local controller are configured to control data movement between the computation units, the first memory device, and the second memory device.

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.

Abstract: Techniques described herein perform spherical PIP analysis by detecting whether a test ray (defined by a test point (TP) and a point (EP) that is external to a spherical polygon) crosses edge arcs (“edges”) of the polygon based on relative orientations of vertices of the test ray and edges. A classifier vector (CV) for a test ray is calculated based on the cross-product of the TP and the EP. Using the CV, the orientation of each vertex of the polygon with respect to the test ray is determined. Candidate edges having vertices with opposite orientations with respect to the test ray are identified. Crossing edges are determine by calculating CVs for each candidate edge, and determining orientations of the TP and EP with respect to each candidate edge. A set of crossing edges is determined, where the TP and the EP have opposite orientations with respect to each crossing edge.

Abstract: A method for performing a matrix multiplication operation is provided. The method includes: obtaining a matrix B1, a matrix A2, and an index matrix, wherein the index matrix comprises indexes, in a matrix A1, of elements in the matrix A2; generating m matrices B2 based on the index matrix and the matrix B1, wherein the m matrices B2 are all matrices with t rows and n columns, and each row of each matrix B2 is a row indicated in the matrix B1 by a corresponding element in the index matrix; and generating a matrix C based on the matrix A2 and the m matrices B2, wherein the matrix C is a product of the matrix A1 and the matrix B1.

Abstract: Systems and methods that facilitate motion formalism utilizing quantum computing, to compute matrix operators in terms of commutators between qubit operators and measurements on the quantum hardware, wherein the commutators are computed utilizing symbolic calculus. Embodiments reduce computational cost of generalized eigenvalue synthesis relying on symbolic calculus and parallelization. Embodiments disclosed herein can also develop estimators of excited-states properties, considering constants of motion (e.g. spin) and non-constants of motions (e.g. dipoles, density matrices).